mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Moved forwarding logic into controller
This commit is contained in:
David Harris
parent
8196ab20be
commit
2c2f692f3a
@ -28,9 +28,9 @@
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module hazard import cvw::*; #(parameter cvw_t P) (
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input logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
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input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
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input logic StructuralStallD,
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input logic LSUStallM, IFUStallF,
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input logic FCvtIntStallD, FPUStallD,
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input logic FPUStallD,
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input logic DivBusyE, FDivBusyE,
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input logic wfiM, IntPendingM,
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// Stall & flush outputs
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@ -82,7 +82,7 @@ module hazard import cvw::*; #(parameter cvw_t P) (
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// The IFU stalls the entire pipeline rather than just Fetch to avoid complications with instructions later in the pipeline causing Exceptions
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// A trap could be asserted at the start of a IFU/LSU stall, and should flush the memory operation
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assign StallFCause = '0;
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FPUStallD) & ~FlushDCause;
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assign StallDCause = (StructuralStallD | FPUStallD) & ~FlushDCause;
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assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause;
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assign StallMCause = WFIStallM & ~FlushMCause;
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// Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
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@ -27,8 +27,8 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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input logic [WIDTH-1:0] A, B, // Operands
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module alu import cvw::*; #(parameter cvw_t P) (
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input logic [P.XLEN-1:0] A, B, // Operands
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input logic W64, // W64-type instruction
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input logic SubArith, // Subtraction or arithmetic shift
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input logic [2:0] ALUSelect, // ALU mux select signal
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@ -37,14 +37,14 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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input logic [2:0] Funct3, // For BMU decoding
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic BMUActiveE, // Bit manipulation instruction being executed
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output logic [WIDTH-1:0] ALUResult, // ALU result
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output logic [WIDTH-1:0] Sum); // Sum of operands
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output logic [P.XLEN-1:0] ALUResult, // ALU result
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output logic [P.XLEN-1:0] Sum); // Sum of operands
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// CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction.
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// FullResult = ALU result before adjusting for a RV64 w-suffix instruction.
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logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals
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logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux
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logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux
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logic [P.XLEN-1:0] CondMaskInvB, Shift, FullResult, PreALUResult; // Intermediate Signals
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logic [P.XLEN-1:0] CondMaskB; // Result of B mask select mux
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logic [P.XLEN-1:0] CondShiftA; // Result of A shifted select mux
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logic Carry, Neg; // Flags: carry out, negative
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logic LT, LTU; // Less than, Less than unsigned
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logic Asign, Bsign; // Sign bits of A, B
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@ -53,7 +53,7 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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// CondMaskB is B for add/sub, or a masked version of B for certain bit manipulation instructions
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// CondShiftA is A for add/sub or a shifted version of A for shift-and-add BMU instructions
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assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB;
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assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith};
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assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(P.XLEN-1){1'b0}}, SubArith};
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// Shifts (configurable for rotation)
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shifter #(P) sh(.A, .Amt(B[P.LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2]));
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@ -62,9 +62,9 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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// Overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign of A.
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// LT is simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
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assign Neg = Sum[WIDTH-1];
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assign Asign = A[WIDTH-1];
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assign Bsign = B[WIDTH-1];
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assign Neg = Sum[P.XLEN-1];
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assign Asign = A[P.XLEN-1];
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assign Bsign = B[P.XLEN-1];
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg;
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assign LTU = ~Carry;
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@ -73,21 +73,22 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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case (ALUSelect)
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3'b000: FullResult = Sum; // add or sub (including address generation)
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3'b001: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu
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3'b010: FullResult = {{(P.XLEN-1){1'b0}}, LT}; // slt
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3'b011: FullResult = {{(P.XLEN-1){1'b0}}, LTU}; // sltu
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3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv
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3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
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3'b101: FullResult = (P.ZBS_SUPPORTED | P.ZBB_SUPPORTED) ? {{(P.XLEN-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported)
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3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
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3'b111: FullResult = A & CondMaskInvB; // and, bclr
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endcase
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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if (P.XLEN == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign PreALUResult = FullResult;
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// Final Result B instruction select mux
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if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED) begin : bitmanipalu
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bitmanipalu #(P, WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActiveE,
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bitmanipalu #(P) balu(
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.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActiveE,
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.Funct3, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,
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.CondMaskB, .CondShiftA, .ALUResult);
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end else begin
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@ -27,9 +27,8 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module bitmanipalu import cvw::*; #(parameter cvw_t P,
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parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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module bitmanipalu import cvw::*; #(parameter cvw_t P) (
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input logic [P.XLEN-1:0] A, B, // Operands
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input logic W64, // W64-type instruction
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input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
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input logic [2:0] ZBBSelect, // ZBB mux select signal
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@ -38,37 +37,37 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P,
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input logic LTU, // less than unsigned flag
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input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage
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input logic BMUActiveE, // Bit manipulation instruction being executed
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input logic [WIDTH-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals
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output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
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output logic [WIDTH-1:0] ALUResult); // Result
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input logic [P.XLEN-1:0] PreALUResult, FullResult,// PreALUResult, FullResult signals
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output logic [P.XLEN-1:0] CondMaskB, // B is conditionally masked for ZBS instructions
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output logic [P.XLEN-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions
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output logic [P.XLEN-1:0] ALUResult); // Result
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logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result
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logic [WIDTH-1:0] MaskB; // BitMask of B
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logic [WIDTH-1:0] RevA; // Bit-reversed A
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logic [P.XLEN-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result
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logic [P.XLEN-1:0] MaskB; // BitMask of B
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logic [P.XLEN-1:0] RevA; // Bit-reversed A
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logic Rotate; // Indicates if it is Rotate instruction
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logic Mask; // Indicates if it is ZBS instruction
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logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction
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logic [1:0] PreShiftAmt; // Amount to Pre-Shift A
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logic [WIDTH-1:0] CondZextA; // A Conditional Extend Intermediary Signal
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logic [WIDTH-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity
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logic [P.XLEN-1:0] CondZextA; // A Conditional Extend Intermediary Signal
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logic [P.XLEN-1:0] ABMU, BBMU; // Gated data inputs to reduce BMU activity
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// gate data inputs to BMU to only operate when BMU is active
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assign ABMU = A & {WIDTH{BMUActiveE}};
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assign BBMU = B & {WIDTH{BMUActiveE}};
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assign ABMU = A & {P.XLEN{BMUActiveE}};
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assign BBMU = B & {P.XLEN{BMUActiveE}};
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// Extract control signals from bitmanip ALUControl.
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assign {Mask, PreShift} = BALUControl[1:0];
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// Mask Generation Mux
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if (P.ZBS_SUPPORTED) begin: zbsdec
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decoder #($clog2(WIDTH)) maskgen(BBMU[$clog2(WIDTH)-1:0], MaskB);
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mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB);
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decoder #($clog2(P.XLEN)) maskgen(BBMU[$clog2(P.XLEN)-1:0], MaskB);
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mux2 #(P.XLEN) maskmux(B, MaskB, Mask, CondMaskB);
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end else assign CondMaskB = B;
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// 0-3 bit Pre-Shift Mux
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if (P.ZBA_SUPPORTED) begin: zbapreshift
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if (WIDTH == 64) begin
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if (P.XLEN == 64) begin
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mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA);
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end else assign CondZextA = A;
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assign PreShiftAmt = Funct3[2:1] & {2{PreShift}};
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@ -80,17 +79,17 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P,
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// Bit reverse needed for some ZBB, ZBC instructions
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if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
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bitreverse #(WIDTH) brA(.A(ABMU), .RevA);
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bitreverse #(P.XLEN) brA(.A(ABMU), .RevA);
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end
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// ZBC Unit
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if (P.ZBC_SUPPORTED) begin: zbc
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zbc #(WIDTH) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
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zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
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end else assign ZBCResult = 0;
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// ZBB Unit
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if (P.ZBB_SUPPORTED) begin: zbb
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zbb #(WIDTH) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
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zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect, .ZBBResult);
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end else assign ZBBResult = 0;
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// Result Select Mux
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@ -39,10 +39,14 @@ module controller import cvw::*; #(parameter cvw_t P) (
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output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
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output logic JumpD, // Jump instruction
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output logic BranchD, // Branch instruction
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// Execute stage control signals
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output logic StructuralStallD, // Structural stalls detected by controller
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output logic LoadStallD, // Structural stalls for load, sent to performance counters
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output logic [4:0] Rs1D, Rs2D, // Register sources to read in Decode or Execute stage
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// Execute stage control signals
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input logic StallE, FlushE, // Stall, flush Execute stage
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input logic [1:0] FlagsE, // Comparison flags ({eq, lt})
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input logic FWriteIntE, // Write integer register, coming from FPU controller
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input logic FCvtIntE, // FPU convert float to int
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output logic PCSrcE, // Select signal to choose next PC (for datapath and Hazard unit)
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output logic ALUSrcAE, ALUSrcBE, // ALU operands
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output logic ALUResultSrcE, // Selects result to pass on to Memory stage
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@ -65,7 +69,7 @@ module controller import cvw::*; #(parameter cvw_t P) (
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output logic [3:0] CMOpM, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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output logic IFUPrefetchE, // instruction prefetch
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output logic LSUPrefetchM, // data prefetch
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output logic [1:0] ForwardAE, ForwardBE, // Select signals for forwarding multiplexers
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// Memory stage control signals
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input logic StallM, FlushM, // Stall, flush Memory stage
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output logic [1:0] MemRWE, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write
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@ -83,14 +87,16 @@ module controller import cvw::*; #(parameter cvw_t P) (
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output logic [2:0] ResultSrcW, // Select source of result to write back to register file
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// Stall during CSRs
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output logic CSRWriteFenceM, // CSR write or fence instruction; needs to flush the following instructions
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output logic StoreStallD // Store (memory write) causes stall
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output logic [4:0] RdE, RdM, // Pipelined destination registers
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// Forwarding controls
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output logic [4:0] RdW // Register destinations in Execute, Memory, or Writeback stage
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);
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logic [4:0] Rs1E, Rs2E; // pipelined register sources
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logic [6:0] OpD; // Opcode in Decode stage
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logic [2:0] Funct3D; // Funct3 field in Decode stage
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logic [6:0] Funct7D; // Funct7 field in Decode stage
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logic [4:0] Rs1D, Rs2D, RdD; // Rs1/2 source register / dest reg in Decode stage
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logic [4:0] RdD; // Rs1/2 source register / dest reg in Decode stage
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`define CTRLW 24
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@ -146,6 +152,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
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logic [3:0] CMOpD, CMOpE; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero
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logic IFUPrefetchD; // instruction prefetch
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logic LSUPrefetchD, LSUPrefetchE; // data prefetch
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logic AMOStallD, CMOStallD; // Structural hazards from atomic and cache management ops
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logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage
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logic FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read
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// Extract fields
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assign OpD = InstrD[6:0];
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@ -394,6 +403,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
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flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE,
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{ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, IFUPrefetchD, LSUPrefetchD, InstrValidD},
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{ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, IFUPrefetchE, LSUPrefetchE, InstrValidE});
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flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
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flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
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flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
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// Branch Logic
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// The comparator handles both signed and unsigned branches using BranchSignedE
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@ -415,22 +427,45 @@ module controller import cvw::*; #(parameter cvw_t P) (
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flopenrc #(25) controlregM(clk, reset, FlushM, ~StallM,
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{RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE, CMOpE, LSUPrefetchE},
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{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM, CMOpM, LSUPrefetchM});
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flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
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// Writeback stage pipeline control register
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flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
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{RegWriteM, ResultSrcM, IntDivM},
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{RegWriteW, ResultSrcW, IntDivW});
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flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
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// Flush F, D, and E stages on a CSR write or Fence.I or SFence.VMA
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assign CSRWriteFenceM = CSRWriteM | FenceM;
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// Forwarding logic
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always_comb begin
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ForwardAE = 2'b00;
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ForwardBE = 2'b00;
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if (Rs1E != 5'b0)
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if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
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else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
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if (Rs2E != 5'b0)
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if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
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else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
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end
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// Stall on dependent operations that finish in Mem Stage and can't bypass in time
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assign MatchDE = ((Rs1D == RdE) | (Rs2D == RdE)) & (RdE != 5'b0); // Decode-stage instruction source depends on result from execute stage instruction
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assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt
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assign LoadStallD = (MemReadE|SCE) & MatchDE;
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assign MDUStallD = MDUE & MatchDE; // Int mult/div is at least two cycle latency, even when coming from the FDIV
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assign CSRRdStallD = CSRReadE & MatchDE;
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// the synchronous DTIM cannot read immediately after write
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// a cache cannot read or write immediately after a write
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// atomic operations are also detected as MemRWD[1]
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// atomic operations are also detected as MemRWD[1] ***check; seems like & MemRWE
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// *** RT: Remove this after updating the cache.
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// *** RT: Check that atomic after atomic works correctly.
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//assign StoreStallD = ((|CMOpE)) & ((|CMOpD));
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logic AMOHazard;
|
||||
assign AMOHazard = &MemRWE & MemRWD[1];
|
||||
assign StoreStallD = ((|CMOpE) & (|CMOpD)) | AMOHazard;
|
||||
assign AMOStallD = &MemRWE & MemRWD[1]; // Read after atomic operation causes structural hazard
|
||||
assign CMOStallD = (|CMOpE) & (|CMOpD); // CMO op after CMO op causes structural hazard ***explain, why doesn't interact with read/write
|
||||
|
||||
// Structural hazard causes stall if any of these events occur
|
||||
assign StructuralStallD = LoadStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | AMOStallD | CMOStallD;
|
||||
endmodule
|
||||
|
||||
@ -32,6 +32,7 @@ module datapath import cvw::*; #(parameter cvw_t P) (
|
||||
// Decode stage signals
|
||||
input logic [2:0] ImmSrcD, // Selects type of immediate extension
|
||||
input logic [31:0] InstrD, // Instruction in Decode stage
|
||||
input logic [4:0] Rs1D, Rs2D, // Source registers
|
||||
// Execute stage signals
|
||||
input logic [P.XLEN-1:0] PCE, // PC in Execute stage
|
||||
input logic [P.XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage)
|
||||
@ -68,9 +69,8 @@ module datapath import cvw::*; #(parameter cvw_t P) (
|
||||
input logic [P.XLEN-1:0] CSRReadValW, // CSR read result
|
||||
input logic [P.XLEN-1:0] MDUResultW, // MDU (Multiply/divide unit) result
|
||||
input logic [P.XLEN-1:0] FIntDivResultW, // FPU's integer divide result
|
||||
input logic [4:0] RdW // Destination register
|
||||
// Hazard Unit signals
|
||||
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, // Register sources to read in Decode or Execute stage
|
||||
output logic [4:0] RdE, RdM, RdW // Register destinations in Execute, Memory, or Writeback stage
|
||||
);
|
||||
|
||||
// Fetch stage signals
|
||||
@ -94,9 +94,6 @@ module datapath import cvw::*; #(parameter cvw_t P) (
|
||||
logic [P.XLEN-1:0] MulDivResultW; // Multiply always comes from MDU. Divide could come from MDU or FPU (when using fdivsqrt for integer division)
|
||||
|
||||
// Decode stage
|
||||
assign Rs1D = InstrD[19:15];
|
||||
assign Rs2D = InstrD[24:20];
|
||||
assign RdD = InstrD[11:7];
|
||||
regfile #(P.XLEN, P.E_SUPPORTED) regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, ResultW, R1D, R2D);
|
||||
extend #(P) ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ImmExtD);
|
||||
|
||||
@ -104,28 +101,23 @@ module datapath import cvw::*; #(parameter cvw_t P) (
|
||||
flopenrc #(P.XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
|
||||
flopenrc #(P.XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
|
||||
flopenrc #(P.XLEN) ImmExtEReg(clk, reset, FlushE, ~StallE, ImmExtD, ImmExtE);
|
||||
flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
|
||||
flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
|
||||
flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
|
||||
|
||||
mux3 #(P.XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE);
|
||||
mux3 #(P.XLEN) fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE);
|
||||
comparator #(P.XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE);
|
||||
mux2 #(P.XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
|
||||
mux2 #(P.XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
|
||||
alu #(P, P.XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, ALUResultE, IEUAdrE);
|
||||
alu #(P) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, BALUControlE, BMUActiveE, ALUResultE, IEUAdrE);
|
||||
mux2 #(P.XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
|
||||
mux2 #(P.XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
|
||||
|
||||
// Memory stage pipeline register
|
||||
flopenrc #(P.XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
|
||||
flopenrc #(P.XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
|
||||
flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);
|
||||
flopenrc #(P.XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM);
|
||||
|
||||
// Writeback stage pipeline register and logic
|
||||
flopenrc #(P.XLEN) IFResultWReg(clk, reset, FlushW, ~StallW, IFResultM, IFResultW);
|
||||
flopenrc #(5) RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
|
||||
|
||||
// floating point inputs: FIntResM comes from fclass, fcmp, fmv; FCvtIntResW comes from fcvt
|
||||
if (P.F_SUPPORTED) begin:fpmux
|
||||
|
||||
@ -1,62 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// forward.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
|
||||
// Created: 9 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Determine datapath forwarding
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.2.2.3)
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module forward(
|
||||
// Detect hazards
|
||||
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers
|
||||
input logic MemReadE, MDUE, CSRReadE, // Execute stage instruction is a load (MemReadE), divide (MDUE), or CSR read (CSRReadE)
|
||||
input logic RegWriteM, RegWriteW, // Instruction in Memory or Writeback stage writes register file
|
||||
input logic FCvtIntE, // FPU convert float to int
|
||||
input logic SCE, // Store Conditional instruction
|
||||
// Forwarding controls
|
||||
output logic [1:0] ForwardAE, ForwardBE, // Select signals for forwarding multiplexers
|
||||
output logic FCvtIntStallD, LoadStallD, MDUStallD, CSRRdStallD // Stall due to conversion, load, multiply/divide, CSR read
|
||||
);
|
||||
|
||||
logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage
|
||||
|
||||
always_comb begin
|
||||
ForwardAE = 2'b00;
|
||||
ForwardBE = 2'b00;
|
||||
if (Rs1E != 5'b0)
|
||||
if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
|
||||
else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
|
||||
|
||||
if (Rs2E != 5'b0)
|
||||
if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
|
||||
else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
|
||||
end
|
||||
|
||||
// Stall on dependent operations that finish in Mem Stage and can't bypass in time
|
||||
assign MatchDE = ((Rs1D == RdE) | (Rs2D == RdE)) & (RdE != 5'b0); // Decode-stage instruction source depends on result from execute stage instruction
|
||||
assign FCvtIntStallD = FCvtIntE & MatchDE; // FPU to Integer transfers have single-cycle latency except fcvt
|
||||
assign LoadStallD = (MemReadE|SCE) & MatchDE;
|
||||
assign MDUStallD = MDUE & MatchDE; // Int mult/div is at least two cycle latency, even when coming from the FDIV
|
||||
assign CSRRdStallD = CSRReadE & MatchDE;
|
||||
endmodule
|
||||
@ -73,8 +73,8 @@ module ieu import cvw::*; #(parameter cvw_t P) (
|
||||
// Hazard unit signals
|
||||
input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit
|
||||
input logic FlushD, FlushE, FlushM, FlushW, // Flush signals
|
||||
output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit
|
||||
output logic MDUStallD, CSRRdStallD, StoreStallD,
|
||||
output logic StructuralStallD, // IEU detects structural hazard in Decode stage
|
||||
output logic LoadStallD, // Structural stalls for load, sent to performance counters
|
||||
output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction
|
||||
output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions
|
||||
);
|
||||
@ -94,7 +94,7 @@ module ieu import cvw::*; #(parameter cvw_t P) (
|
||||
logic SubArithE; // Subtraction or arithmetic shift
|
||||
|
||||
// Forwarding signals
|
||||
logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers
|
||||
logic [4:0] Rs1D, Rs2D; // Source registers
|
||||
logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers
|
||||
logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages
|
||||
logic MemReadE, CSRReadE; // Load, CSRRead instruction
|
||||
@ -104,25 +104,23 @@ module ieu import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
controller #(P) c(
|
||||
.clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD,
|
||||
.IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
|
||||
.IllegalIEUFPUInstrD, .IllegalBaseInstrD,
|
||||
.StructuralStallD, .LoadStallD, .Rs1D, .Rs2D,
|
||||
.StallE, .FlushE, .FlagsE, .FWriteIntE,
|
||||
.PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE,
|
||||
.Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE,
|
||||
.BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
|
||||
.BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE,
|
||||
.FCvtIntE, .ForwardAE, .ForwardBE, .CMOpM, .IFUPrefetchE, .LSUPrefetchM,
|
||||
.StallM, .FlushM, .MemRWE, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
|
||||
.RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
|
||||
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD);
|
||||
.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM,
|
||||
.RdW, .RdE, .RdM);
|
||||
|
||||
datapath #(P) dp(
|
||||
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
|
||||
.clk, .reset, .ImmSrcD, .InstrD, .Rs1D, .Rs2D, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE,
|
||||
.Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE,
|
||||
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE,
|
||||
.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
|
||||
.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
|
||||
|
||||
forward fw(
|
||||
.Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
|
||||
.MemReadE, .MDUE, .CSRReadE, .RegWriteM, .RegWriteW,
|
||||
.FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
|
||||
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW);
|
||||
endmodule
|
||||
|
||||
@ -54,7 +54,6 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
||||
input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode
|
||||
// inputs for performance counters
|
||||
input logic LoadStallD,
|
||||
input logic StoreStallD,
|
||||
input logic ICacheStallF,
|
||||
input logic DCacheStallM,
|
||||
input logic BPDirPredWrongM,
|
||||
@ -275,7 +274,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
if (P.ZICNTR_SUPPORTED) begin:counters
|
||||
csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
|
||||
.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
|
||||
.InstrValidNotFlushedM, .LoadStallD, .CSRWriteM, .CSRMWriteM,
|
||||
.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM,
|
||||
.InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
|
||||
|
||||
@ -32,7 +32,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
||||
input logic clk, reset,
|
||||
input logic StallE, StallM,
|
||||
input logic FlushM,
|
||||
input logic InstrValidNotFlushedM, LoadStallD, StoreStallD,
|
||||
input logic InstrValidNotFlushedM, LoadStallD,
|
||||
input logic CSRMWriteM, CSRWriteM,
|
||||
input logic BPDirPredWrongM,
|
||||
input logic BTAWrongM,
|
||||
@ -75,7 +75,6 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
||||
logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0];
|
||||
logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0];
|
||||
logic LoadStallE, LoadStallM;
|
||||
logic StoreStallE, StoreStallM;
|
||||
logic [P.COUNTERS-1:0] WriteHPMCOUNTERM;
|
||||
logic [P.COUNTERS-1:0] CounterEvent;
|
||||
logic [63:0] HPMCOUNTERPlusM[P.COUNTERS-1:0];
|
||||
@ -83,8 +82,8 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
||||
genvar i;
|
||||
|
||||
// Interface signals
|
||||
flopenrc #(2) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d({StoreStallD, LoadStallD}), .q({StoreStallE, LoadStallE})); // don't flush the load stall during a load stall.
|
||||
flopenrc #(2) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d({StoreStallE, LoadStallE}), .q({StoreStallM, LoadStallM}));
|
||||
flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
|
||||
flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
|
||||
|
||||
// Determine when to increment each counter
|
||||
assign CounterEvent[0] = 1'b1; // MCYCLE always increments
|
||||
@ -100,7 +99,7 @@ module csrc import cvw::*; #(parameter cvw_t P) (
|
||||
assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address
|
||||
assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
|
||||
assign CounterEvent[11] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed.
|
||||
assign CounterEvent[12] = StoreStallM; // Store Stall
|
||||
assign CounterEvent[12] = 0; // depricated Store Stall
|
||||
assign CounterEvent[13] = DCacheAccess; // data cache access
|
||||
assign CounterEvent[14] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss
|
||||
assign CounterEvent[15] = DCacheStallM; // d cache miss cycles
|
||||
|
||||
@ -45,7 +45,6 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
||||
// processor events for performance counter logging
|
||||
input logic FRegWriteM, // instruction will write floating-point registers
|
||||
input logic LoadStallD, // load instruction is stalling
|
||||
input logic StoreStallD, // store instruction is stalling
|
||||
input logic ICacheStallF, // I cache stalled
|
||||
input logic DCacheStallM, // D cache stalled
|
||||
input logic BPDirPredWrongM, // branch predictor guessed wrong direction
|
||||
@ -133,7 +132,7 @@ module privileged import cvw::*; #(parameter cvw_t P) (
|
||||
.InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM,
|
||||
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
||||
.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD,
|
||||
.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
|
||||
.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM,
|
||||
.sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE,
|
||||
.IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
|
||||
|
||||
@ -75,7 +75,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
logic PCSrcE;
|
||||
logic CSRWriteFenceM;
|
||||
logic DivBusyE;
|
||||
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
|
||||
logic StructuralStallD;
|
||||
logic LoadStallD;
|
||||
logic SquashSCW;
|
||||
logic MDUActiveE; // Mul/Div instruction being executed
|
||||
logic ENVCFG_ADUE; // HPTW A/D Update enable
|
||||
@ -95,7 +96,6 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
logic FCvtIntW;
|
||||
logic FDivBusyE;
|
||||
logic FRegWriteM;
|
||||
logic FCvtIntStallD;
|
||||
logic FpLoadStoreM;
|
||||
logic [4:0] SetFflagsM;
|
||||
logic [P.XLEN-1:0] FIntDivResultW;
|
||||
@ -211,8 +211,8 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW,
|
||||
// hazards
|
||||
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .PCSrcE,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD);
|
||||
.StructuralStallD, .LoadStallD, .PCSrcE,
|
||||
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM);
|
||||
|
||||
lsu #(P) lsu(
|
||||
.clk, .reset, .StallM, .FlushM, .StallW, .FlushW,
|
||||
@ -266,9 +266,9 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
// global stall and flush control
|
||||
hazard #(P) hzu(
|
||||
.BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
|
||||
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
|
||||
.StructuralStallD,
|
||||
.LSUStallM, .IFUStallF,
|
||||
.FCvtIntStallD, .FPUStallD,
|
||||
.FPUStallD,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.wfiM, .IntPendingM,
|
||||
// Stall & flush outputs
|
||||
@ -284,7 +284,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM,
|
||||
.RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF,
|
||||
.InstrValidM, .CommittedM, .CommittedF,
|
||||
.FRegWriteM, .LoadStallD, .StoreStallD,
|
||||
.FRegWriteM, .LoadStallD,
|
||||
.BPDirPredWrongM, .BTAWrongM, .BPWrongM,
|
||||
.RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user