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Merge branch 'openhwgroup:main' into main

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Jordan Carlin 2024-01-12 19:43:01 -08:00 committed by GitHub
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7 changed files with 40 additions and 14 deletions
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21
bin/wally-tool-chain-install.sh
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@ -137,6 +137,27 @@ sudo make install
# package manager. Sail has so many dependencies that it can be difficult to install.
# This script works for Ubuntu.
# Alex Solomatnikov found these commands worked to build Sail for Centos 8 on 1/12/24
#sudo su -
#dnf install ocaml.x86_64
#pip3 install z3-solver
#wget https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh
#sh install.sh
#opam init
#exit
#ocaml -version
#opam switch create 5.1.0
#eval $(opam config env)
#git clone --recurse-submodules git@github.com:riscv/sail-riscv.git
#cd sail-riscv
#make
#ARCH=RV32 make
#ARCH=RV64 make
#git log -1
#cp -p c_emulator/riscv_sim_RV* /tools/sail-riscv/d7a3d8012fd579f40e53a29569141d72dd5e0c32/bin/.
# This was an earlier attemp to prepare to install Sail on RedHat 8
# Do these commands only for RedHat / Rocky 8 to build from source.
#cd $RISCV
#git clone https://github.com/Z3Prover/z3.git

2
config/rv64gc/config.vh
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@ -107,7 +107,7 @@ localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF;
localparam BOOTROM_PRELOAD = 1'b0;
localparam UNCORE_RAM_SUPPORTED = 1'b1;
localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF;
localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF;
localparam UNCORE_RAM_PRELOAD = 1'b0;
localparam EXT_MEM_SUPPORTED = 1'b0;
localparam logic [63:0] EXT_MEM_BASE = 64'h80000000;

11
src/ieu/alu.sv
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@ -101,11 +101,16 @@ module alu import cvw::*; #(parameter cvw_t P) (
// Zicond block
if (P.ZICOND_SUPPORTED) begin: zicond
logic BZero, KillB;
logic BZero;
assign BZero = (B == 0); // check if rs2 = 0
// Create a signal that is 0 when czero.* instruction should clear result
// If B = 0 for czero.eqz or if B != 0 for czero.nez
assign KillB = BZero & CZero[0] | ~BZero & CZero[1];
assign ZeroCondMaskInvB = |CZero ? {P.XLEN{~KillB}} : CondMaskInvB; // extend to full width
always_comb
case (CZero)
2'b01: ZeroCondMaskInvB = {P.XLEN{~BZero}}; // czero.eqz: kill if B = 0
2'b10: ZeroCondMaskInvB = {P.XLEN{BZero}}; // czero.nez: kill if B != 0
default: ZeroCondMaskInvB = CondMaskInvB; // otherwise normal behavior
endcase
end else assign ZeroCondMaskInvB = CondMaskInvB; // no masking if Zicond is not supported
endmodule

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-01.S
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@ -87,8 +87,8 @@ test_cases:
.8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
# second page table to check context switches with satp
.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
# test 11.3.1.1.2 write values to Paddrs in each page
# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
@ -192,7 +192,7 @@ test_cases:
# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
.8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping
# test 11.3.1.4.2 Test Global mapping

6
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-svnapot-svpbmt-01.S
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@ -108,8 +108,8 @@ test_cases:
.8byte 0x0000000080016FF8, 0x00000000200804CF, write64_test# Vaddr 0xFFFFFFFFFFFFF000, Paddr 0x80201000 aligned kilopage
# second page table to check context switches with satp
.8byte 0x8FFFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
.8byte 0x8FFFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
.8byte 0x87FFF000, 0x200000CF, write64_test# Vaddr 0x0, Paddr 0x80000000 aligned gigapage
.8byte 0x87FFF010, 0x200000CF, write64_test# Vaddr 0x8000_0000, Paddr 0x80000000: aligned gigapage (program and data memory so we can execute without jumping around)
# test 11.3.1.1.2 write values to Paddrs in each page
# each of these values is used for 11.3.1.1.3 and some other tests, specified in the comments.
@ -249,7 +249,7 @@ test_cases:
# test 11.3.1.4.1 SATP ASID and PPN fields (test having two page tables with different ASID)
// *** .8byte 0xFFFFFFFFFFFFF888, 0x0220DEADBEEF0099, write64_test # write identical value to global PTE to make sure it's still in the TLB
.8byte 0x8FFFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
.8byte 0x87FFF, 0x11, goto_sv39 # go to SV39 on a second, very minimal page table
.8byte 0x200AB0, 0x0000DEADBEEF0000, read64_test # Read success of old written value from a new page table mapping
# test 11.3.1.4.2 Test Global mapping

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-01.S
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@ -113,7 +113,7 @@ test_cases:
.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2
.8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2
.8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3
.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
.8byte 0x80203AA0, 0x0440DEADBEEF0BB0, write64_test # 11.3.1.3.7
# test 11.3.1.1.3 read values back from Paddrs without translation (this also verifies the previous test)
@ -187,7 +187,7 @@ test_cases:
# test 11.3.1.3.5 eXecute flag
# executes on pages with X = 1 already tested in 11.3.1.3.1
.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0
.8byte 0x010087888000, 0x2, executable_test # execute fault when X=0
# In the following two tests, SVADU is not supported, so the software handles the A/D bits
# Since SVADU is 0, Accesses to A/D=0 causes a fault for the trap handler to fix those bits

4
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S
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@ -113,7 +113,7 @@ test_cases:
.8byte 0x80200AC0, 0x0990DEADBEEF0033, write64_test # 11.3.1.3.2
.8byte 0x80200130, 0x0110DEADBEEF0077, write64_test # 11.3.1.3.2
.8byte 0x85212348, 0x0330DEADBEEF0440, write64_test # 11.3.1.3.3
.8byte 0x88888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
.8byte 0x87888000, 0x0000806711100393, write64_test # 11.3.1.3.5 write same executable code
.8byte 0x80203658, 0xDEADBEEFDEADBEEF, write64_test # 11.3.1.3.7(a)
#.8byte 0x85bc0ab0, 0x0123456789abcdf0, write64_test # 11.3.1.1.4
@ -188,7 +188,7 @@ test_cases:
# test 11.3.1.3.5 eXecute flag
# executes on pages with X = 1 already tested in 11.3.1.3.1
.8byte 0x010088888000, 0x2, executable_test # execute fault when X=0
.8byte 0x010087888000, 0x2, executable_test # execute fault when X=0
# In the following two tests, SVADU is supported, so the hardware handles the A/D bits