Clarified names in cacheway.

This commit is contained in:
Rose Thompson 2023-11-27 12:56:11 -06:00
parent d7ef490c12
commit c3da4c3c31

10
src/cache/cacheway.sv vendored
View File

@ -65,7 +65,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
logic [LINELEN-1:0] ReadDataLine;
logic [TAGLEN-1:0] ReadTag;
logic Dirty;
logic SelTag;
logic SelDirty;
logic SelectedWriteWordEn;
logic [LINELEN/8-1:0] FinalByteMask;
logic SetValidEN, ClearValidEN;
@ -78,7 +78,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
if (!READ_ONLY_CACHE) begin:flushlogic
logic FlushWayEn;
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelDirty);
// FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
// coverage off -item e 1 -fecexprrow 3
@ -86,11 +86,11 @@ module cacheway import cvw::*; #(parameter cvw_t P,
assign FlushWayEn = FlushWay & SelFlush;
assign SelNonHit = FlushWayEn | SelWay;
end else begin:flushlogic // no flush operation for read-only caches.
assign SelTag = VictimWay;
assign SelDirty = VictimWay;
assign SelNonHit = SelWay;
end
mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData);
mux2 #(1) selectedwaymux(HitWay, SelDirty, SelNonHit , SelData);
/////////////////////////////////////////////////////////////////////////////////////////////
// Write Enable demux
@ -117,7 +117,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
// AND portion of distributed tag multiplexer
assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
assign DirtyWay = SelTag & Dirty & ValidWay;
assign DirtyWay = SelDirty & Dirty & ValidWay;
assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
/////////////////////////////////////////////////////////////////////////////////////////////