Commented IROM preloading

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit 9f9bdd62d3e37fcd8ad1b1a39d71694ccf1d74f3
+Subproject commit eb0a3892215ad2384702db02da1551a59701ec67

src/generic/mem/rom1p1r.sv

@@ -47,7 +47,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
 
   initial begin
     if (PRELOAD_ENABLED) begin
-      $readmemh("../../../fpga/src/boot.mem", ROM, 0);
+      $readmemh("$WALLY/fpga/src/boot.mem", ROM, 0);
     end
   end
   

src/ifu/irom.sv

@@ -39,7 +39,9 @@ module irom import cvw::*;  #(parameter cvw_t P) (
   logic [31:0]       RawIROMInstrF;
   logic [2:1]        AdrD;
 
-  rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
+  // preload IROM with the FPGA bootloader by default so that it syntehsizes to something, avoiding having the IEU optimized away because instructions are all 0
+  // the testbench replaces these dummy contents with the actual program of interest during simulation
+  rom1p1r #(ADDR_WDITH, P.XLEN, 1) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
   if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
   else              begin
   // IROM is aligned to XLEN words, but instructions are 32 bits.  Select between the two

synthDC/wallySynthAll.sh

@@ -1,7 +1,8 @@
 # Run all Wally synthesis experiments from chapter 8
-./wallySynth.py --freqsweep 330 --tech sky130 
-./wallySynth.py --freqsweep 870 --tech sky90 
-./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
+# However, trying to run the freqsweeps at the same time maxes out licenses and some runs fail
+#./wallySynth.py --freqsweep 330 --tech sky130 
+#./wallySynth.py --freqsweep 870 --tech sky90 
+#./wallySynth.py --freqsweep 2800 --tech tsmc28psyn --usesram
 ./wallySynth.py --configsweep --tech sky130 --targetfreq 330
 ./wallySynth.py --configsweep --tech sky90 --targetfreq 870
 ./wallySynth.py --configsweep --tech tsmc28psyn --targetfreq 2800 --usesram