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https://github.com/openhwgroup/cvw
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Progress on misaligned load/stores.
This commit is contained in:
Rose Thompson
parent
12763b7297
commit
449abef823
@ -35,9 +35,11 @@ module align import cvw::*; #(parameter cvw_t P) (
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input logic StallM, FlushM,
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input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage
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input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [31:0] ReadDataWordMuxM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
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input logic LSUStallM, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
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input logic DTLBMissM, // ITLB miss, ignore memory request
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input logic DataUpdateDAM, // ITLB miss, ignore memory request
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output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
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output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
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@ -49,10 +51,10 @@ module align import cvw::*; #(parameter cvw_t P) (
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statetype CurrState, NextState;
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logic TakeSpillM, TakeSpillE;
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logic SpillF;
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logic SpillM;
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logic SelSpillF;
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logic SpillSaveF;
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logic [15:0] InstrFirstHalfF;
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logic [LLEN-8:0] ReadDataWordFirstHalfM;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// PC logic
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@ -71,19 +73,23 @@ module align import cvw::*; #(parameter cvw_t P) (
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// spill detection in lsu is more complex than ifu, depends on 3 factors
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// 1) operation size
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// 2) offset
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// 3) access location within the cacheline or is the access is uncached.
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// first consider uncached operations
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// accesses are always aligned to the natural size of the bus (XLEN or AHBW)
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if (P.ICACHE_SUPPORTED) begin
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logic SpillCachedF, SpillUncachedF;
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assign SpillCachedF = &IEUAdrM[$clog2(P.ICACHE_LINELENINBITS/32)+1:1];
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assign SpillUncachedF = IEUAdrM[1]; // *** try to optimize this based on whether the next instruction is 16 bits and by fetching 64 bits in RV64
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assign SpillF = CacheableF ? SpillCachedF : SpillUncachedF;
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end else
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assign SpillF = IEUAdrM[1]; // *** might relax - only spill if next instruction is uncompressed
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// 3) access location within the cacheline
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logic [P.DCACHE_LINELENINBITS/8-1:P.LLEN/8] WordOffsetM;
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logic [P.LLEN/8-1:0] ByteOffsetM;
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logic HalfSpillM, WordSpillM;
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assign {WordOffsetM, ByteOffsetM} = IEUAdrM[P.DCACHE_LINELENINBITS/8-1:0];
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assign HalfSpillM = (WordOffsetM == '1) & Funct3M[1:0] == 2'b01 & ByteOffsetM[0] != 1'b0;
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assign WordSpillM = (WordOffsetM == '1) & Funct3M[1:0] == 2'b10 & ByteOffsetM[1:0] != 2'b00;
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if(P.LLEN == 64) begin
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logic DoubleSpillM;
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assign DoubleSpillM = (WordOffsetM == '1) & Funct3M[1:0] == 2'b11 & ByteOffsetM[2:0] != 3'b00;
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assign SpillM = HalfSpillM | WordOffsetM | DoubleSpillM;
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end else begin
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assign SpillM = HalfSpillM | WordOffsetM;
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end
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// Don't take the spill if there is a stall, TLB miss, or hardware update to the D/A bits
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assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF));
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assign TakeSpillM = SpillM & ~LSUStallM & ~(DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM));
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always_ff @(posedge clk)
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if (reset | FlushM) CurrState <= #1 STATE_READY;
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@ -91,7 +97,7 @@ module align import cvw::*; #(parameter cvw_t P) (
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always_comb begin
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case (CurrState)
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STATE_READY: if (TakeSpillF) NextState = STATE_SPILL;
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STATE_READY: if (TakeSpillM) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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STATE_SPILL: if(StallM) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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@ -99,16 +105,16 @@ module align import cvw::*; #(parameter cvw_t P) (
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endcase
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end
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assign SelSpillF = (CurrState == STATE_SPILL);
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assign SelSpillNextF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallF);
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assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushM;
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assign SelSpillM = (CurrState == STATE_SPILL);
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assign SelSpillE = (CurrState == STATE_READY & TakeSpillM) | (CurrState == STATE_SPILL & LSUStallM);
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assign SpillSaveM = (CurrState == STATE_READY) & TakeSpillM & ~FlushM;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Merge spilled instruction
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// save the first 2 bytes
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flopenr #(16) SpillInstrReg(clk, reset, SpillSaveF, InstrRawF[15:0], InstrFirstHalfF);
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flopenr #(P.LLEN-8) SpillDataReg(clk, reset, SpillSaveM, ReadDataWordMuxM[LLEN-1:8], ReadDataWordFirstHalfM);
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// merge together
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mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalfF}, SpillF, PostSpillInstrRawF);
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@ -234,6 +234,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
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// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
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// **** create config to support DTIM with floating point.
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// Add support for cboz
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dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
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.DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM),
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.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM[P.LLEN/8-1:0]));
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@ -268,8 +269,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign CacheAtomicM = CacheableM & ~SelDTIM ? LSUAtomicM : '0;
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assign FlushDCache = FlushDCacheM & ~(SelHPTW);
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// *** need RT to add support for CMOpM and LSUPrefetchM (DH 7/2/23)
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// *** prefetch can just act as a read operation
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cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMLINES(P.DCACHE_WAYSIZEINBYTES*8/LINELEN),
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.NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(P.LLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache(
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.clk, .reset, .Stall(GatedStallW), .SelBusBeat, .FlushStage(FlushW | IgnoreRequestTLB), .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
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@ -285,6 +284,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
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assign DCacheStallM = CacheStall & ~IgnoreRequestTLB;
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assign CacheBusRW = CacheBusRWTemp;
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// *** add support for cboz
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ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface(
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.HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB),
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.HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB),
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@ -29,125 +29,22 @@
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module subwordread #(parameter LLEN)
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(
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input logic [LLEN-1:0] ReadDataWordMuxM,
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input logic [$clog(LLEN/8)-1:0] PAdrM,
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input logic [2:0] Funct3M,
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input logic FpLoadStoreM,
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input logic BigEndianM,
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output logic [LLEN/2-1:0] ReadDataM
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input logic [LLEN-1:0] ReadDataWordMuxM,
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input logic [2:0] PAdrM,
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input logic [2:0] Funct3M,
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input logic FpLoadStoreM,
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input logic BigEndianM,
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output logic [LLEN-1:0] ReadDataM
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);
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localparam OFFSET_LEN = $clog(LLEN/8);
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localparam HLEN = LLEN/2;
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logic [7:0] ByteM;
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logic [15:0] HalfwordM;
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logic [OFFSET_LEN-1:0] PAdrSwap;
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logic [2:0] PAdrSwap;
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// Funct3M[2] is the unsigned bit. mask upper bits.
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// Funct3M[1:0] is the size of the memory access.
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assign PAdrSwap = PAdrM ^ {OFFSET_LEN{BigEndianM}};
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assign PAdrSwap = PAdrM ^ {3{BigEndianM}};
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if (LLEN == 128) begin:swrmux
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// ByteMe mux
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: ByteM = ReadDataWordMuxM[7:0];
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4'b0001: ByteM = ReadDataWordMuxM[15:8];
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4'b0010: ByteM = ReadDataWordMuxM[23:16];
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4'b0011: ByteM = ReadDataWordMuxM[31:24];
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4'b0100: ByteM = ReadDataWordMuxM[39:32];
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4'b0101: ByteM = ReadDataWordMuxM[47:40];
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4'b0110: ByteM = ReadDataWordMuxM[55:48];
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4'b0111: ByteM = ReadDataWordMuxM[63:56];
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4'b1000: ByteM = ReadDataWordMuxM[71:64];
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4'b1001: ByteM = ReadDataWordMuxM[79:72];
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4'b1010: ByteM = ReadDataWordMuxM[87:80];
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4'b1011: ByteM = ReadDataWordMuxM[95:88];
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4'b1100: ByteM = ReadDataWordMuxM[103:96];
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4'b1101: ByteM = ReadDataWordMuxM[111:104];
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4'b1110: ByteM = ReadDataWordMuxM[119:112];
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4'b1111: ByteM = ReadDataWordMuxM[127:120];
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endcase
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// halfword mux
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: HalfwordM = ReadDataWordMuxM[15:0];
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4'b0001: HalfwordM = ReadDataWordMuxM[23:8];
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4'b0010: HalfwordM = ReadDataWordMuxM[31:16];
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4'b0011: HalfwordM = ReadDataWordMuxM[39:24];
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4'b0100: HalfwordM = ReadDataWordMuxM[47:32];
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4'b0101: HalfwordM = ReadDataWordMuxM[55:40];
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4'b0110: HalfwordM = ReadDataWordMuxM[63:48];
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4'b0111: HalfwordM = ReadDataWordMuxM[71:56];
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4'b1000: HalfwordM = ReadDataWordMuxM[79:64];
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4'b1001: HalfwordM = ReadDataWordMuxM[87:72];
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4'b1010: HalfwordM = ReadDataWordMuxM[95:80];
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4'b1011: HalfwordM = ReadDataWordMuxM[103:88];
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4'b1100: HalfwordM = ReadDataWordMuxM[111:96];
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4'b1101: HalfwordM = ReadDataWordMuxM[119:104];
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4'b1110: HalfwordM = ReadDataWordMuxM[127:112];
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//4'b1111: HalfwordM = {ReadDataWordMuxM[7:0], ReadDataWordMuxM[127:120]}; // *** might be ok to zero extend rather than wrap around
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4'b1111: HalfwordM = {8'b0, ReadDataWordMuxM[127:120]}; // *** might be ok to zero extend rather than wrap around
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endcase
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logic [31:0] WordM;
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: WordM = ReadDataWordMuxM[31:0];
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4'b0001: WordM = ReadDataWordMuxM[39:8];
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4'b0010: WordM = ReadDataWordMuxM[47:16];
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4'b0011: WordM = ReadDataWordMuxM[55:24];
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4'b0100: WordM = ReadDataWordMuxM[63:32];
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4'b0101: WordM = ReadDataWordMuxM[71:40];
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4'b0111: WordM = ReadDataWordMuxM[79:48];
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4'b1000: WordM = ReadDataWordMuxM[87:56];
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4'b1001: WordM = ReadDataWordMuxM[95:64];
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4'b1010: WordM = ReadDataWordMuxM[103:72];
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4'b1011: WordM = ReadDataWordMuxM[111:80];
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4'b1011: WordM = ReadDataWordMuxM[119:88];
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4'b1100: WordM = ReadDataWordMuxM[127:96];
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4'b1101: WordM = {8'b0, ReadDataWordMuxM[127:104]};
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4'b1110: WordM = {16'b0, ReadDataWordMuxM[127:112]};
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4'b1111: WordM = {24'b0, ReadDataWordMuxM[127:120]};
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endcase
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logic [63:0] DblWordM;
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: DblWordMM = ReadDataWordMuxM[63:0];
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4'b0001: DblWordMM = ReadDataWordMuxM[71:8];
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4'b0010: DblWordMM = ReadDataWordMuxM[79:16];
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4'b0011: DblWordMM = ReadDataWordMuxM[87:24];
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4'b0100: DblWordMM = ReadDataWordMuxM[95:32];
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4'b0101: DblWordMM = ReadDataWordMuxM[103:40];
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4'b0111: DblWordMM = ReadDataWordMuxM[111:48];
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4'b1000: DblWordMM = ReadDataWordMuxM[119:56];
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4'b1001: DblWordMM = ReadDataWordMuxM[127:64];
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4'b1010: DblWordMM = {8'b0, ReadDataWordMuxM[103:72]};
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4'b1011: DblWordMM = {16'b0, ReadDataWordMuxM[111:80]};
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4'b1011: DblWordMM = {24'b0, ReadDataWordMuxM[119:88]};
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4'b1100: DblWordMM = {32'b0, ReadDataWordMuxM[127:96]};
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4'b1101: DblWordMM = {40'b0, ReadDataWordMuxM[127:104]};
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4'b1110: DblWordMM = {48'b0, ReadDataWordMuxM[127:112]};
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4'b1111: DblWordMM = {56'b0, ReadDataWordMuxM[127:120]};
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endcase
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// sign extension/ NaN boxing
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{HLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{HLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{HLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b011: ReadDataM = {{HLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
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3'b100: ReadDataM = {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
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3'b101: ReadDataM = {{HLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b110: ReadDataM = {{HLEN-32{1'b0}}, WordM[31:0]}; // lwu
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default: ReadDataM = ReadDataWordMuxM[HLEN-1:0]; // Shouldn't happen
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endcase
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end else if (LLEN == 64) begin:swrmux
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if (LLEN == 64) begin:swrmux
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// ByteMe mux
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always_comb
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case(PAdrSwap[2:0])
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@ -163,55 +60,35 @@ module subwordread #(parameter LLEN)
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// halfword mux
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always_comb
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case(PAdrSwap[2:0])
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3'b000: HalfwordM = ReadDataWordMuxM[15:0];
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3'b001: HalfwordM = ReadDataWordMuxM[23:8];
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3'b010: HalfwordM = ReadDataWordMuxM[31:16];
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3'b011: HalfwordM = ReadDataWordMuxM[39:24];
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3'b100: HalfwordM = ReadDataWordMuxM[47:32];
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3'b011: HalfwordM = ReadDataWordMuxM[55:40];
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3'b110: HalfwordM = ReadDataWordMuxM[63:48];
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3'b011: HalfwordM = {8'b0, ReadDataWordMuxM[63:56]};
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case(PAdrSwap[2:1])
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2'b00: HalfwordM = ReadDataWordMuxM[15:0];
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2'b01: HalfwordM = ReadDataWordMuxM[31:16];
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2'b10: HalfwordM = ReadDataWordMuxM[47:32];
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2'b11: HalfwordM = ReadDataWordMuxM[63:48];
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endcase
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logic [31:0] WordM;
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always_comb
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case(PAdrSwap[2:0])
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3'b000: WordM = ReadDataWordMuxM[31:0];
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3'b001: WordM = ReadDataWordMuxM[39:8];
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3'b010: WordM = ReadDataWordMuxM[47:16];
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3'b011: WordM = ReadDataWordMuxM[55:24];
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3'b100: WordM = ReadDataWordMuxM[63:32];
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3'b101: WordM = {8'b0, ReadDataWordMuxM[63:40]};
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3'b110: WordM = {16'b0, ReadDataWordMuxM[63:48]};
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3'b111: WordM = {24'b0, ReadDataWordMuxM[63:56]};
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case(PAdrSwap[2])
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1'b0: WordM = ReadDataWordMuxM[31:0];
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1'b1: WordM = ReadDataWordMuxM[63:32];
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endcase
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logic [63:0] DblWordM;
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always_comb
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case(PAdrSwap[2:0])
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3'b000: DblWordMM = ReadDataWordMuxM[63:0];
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3'b001: DblWordMM = {8'b0, ReadDataWordMuxM[63:8]};
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3'b010: DblWordMM = {16'b0, ReadDataWordMuxM[63:16]};
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3'b011: DblWordMM = {24'b0, ReadDataWordMuxM[63:24]};
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3'b100: DblWordMM = {32'b0, ReadDataWordMuxM[63:32]};
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3'b101: DblWordMM = {40'b0, ReadDataWordMuxM[63:40]};
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3'b110: DblWordMM = {48'b0, ReadDataWordMuxM[63:48]};
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3'b111: DblWordMM = {56'b0, ReadDataWordMuxM[63:56]};
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endcase
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assign DblWordM = ReadDataWordMuxM[63:0];
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// sign extension/ NaN boxing
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{HLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{HLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{HLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b011: ReadDataM = {{HLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
|
||||
3'b100: ReadDataM = {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu
|
||||
//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
|
||||
3'b101: ReadDataM = {{HLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
|
||||
3'b110: ReadDataM = {{HLEN-32{1'b0}}, WordM[31:0]}; // lwu
|
||||
3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb
|
||||
3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
|
||||
3'b010: ReadDataM = {{LLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
|
||||
3'b011: ReadDataM = {{LLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
|
||||
3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
|
||||
//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
|
||||
3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
|
||||
3'b110: ReadDataM = {{LLEN-32{1'b0}}, WordM[31:0]}; // lwu
|
||||
default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
|
||||
endcase
|
||||
|
||||
@ -227,22 +104,20 @@ module subwordread #(parameter LLEN)
|
||||
|
||||
// halfword mux
|
||||
always_comb
|
||||
case(PAdrSwap[1:0])
|
||||
2'b00: HalfwordM = ReadDataWordMuxM[15:0];
|
||||
2'b01: HalfwordM = ReadDataWordMuxM[23:8];
|
||||
2'b10: HalfwordM = ReadDataWordMuxM[31:16];
|
||||
2'b11: HalfwordM = {8'b0, ReadDataWordMuxM[31:24]};
|
||||
case(PAdrSwap[1])
|
||||
1'b0: HalfwordM = ReadDataWordMuxM[15:0];
|
||||
1'b1: HalfwordM = ReadDataWordMuxM[31:16];
|
||||
endcase
|
||||
|
||||
// sign extension
|
||||
always_comb
|
||||
case(Funct3M)
|
||||
3'b000: ReadDataM = {{HLEN-8{ByteM[7]}}, ByteM}; // lb
|
||||
3'b001: ReadDataM = {{HLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
|
||||
3'b010: ReadDataM = {{HLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
|
||||
3'b000: ReadDataM = {{LLEN-8{ByteM[7]}}, ByteM}; // lb
|
||||
3'b001: ReadDataM = {{LLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
|
||||
3'b010: ReadDataM = {{LLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
|
||||
3'b011: ReadDataM = ReadDataWordMuxM; // fld
|
||||
3'b100: ReadDataM = {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu
|
||||
3'b101: ReadDataM = {{HLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
|
||||
3'b100: ReadDataM = {{LLEN-8{1'b0}}, ByteM[7:0]}; // lbu
|
||||
3'b101: ReadDataM = {{LLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
|
||||
default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
|
||||
endcase
|
||||
end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user