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Removed vivado property from rom1p1r.sv. It's now dynamically added using the FPGA makefile.

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This commit is contained in:
Jacob Pease 2023-12-01 18:59:18 -06:00
parent 0a804e2cc8
commit 7e494f2d3b
2 changed files with 3 additions and 1 deletions
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2
fpga/generator/Makefile
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@ -71,6 +71,8 @@ PreProcessFiles:
sed -i "s/PLIC_SDC_ID.*/PLIC_SDC_ID = 32'd20;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/BPRED_SIZE.*/BPRED_SIZE = 32'd12;/g" ../src/CopiedFiles_do_not_add_to_repo/config/config.vh
sed -i "s/$\$readmemh.*/$\$readmemh(\"..\/..\/..\/fpga\/src\/boot.mem\", ROM, 0);/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
# This line allows the Bootloader to be loaded in a Block RAM on the FPGA
sed -i "s/logic \[DATA_WIDTH-1:0\].*ROM.*/(\* rom_style=\"block\" \*) &/g" ../src/CopiedFiles_do_not_add_to_repo/generic/mem/rom1p1r.sv
$(dst)/%.log: %.tcl
mkdir -p IP

2
src/generic/mem/rom1p1r.sv
View File

@ -33,7 +33,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, DATA_WIDTH = 32, PRELOAD_ENABLED = 0)
);
// Core Memory
(*rom_style="block" *) logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0];
// dh 10/30/23 ROM macros are presently commented out
// because they don't point to a generated ROM