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Removed assign statement inside always block

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David Harris 2023-11-13 07:23:15 -08:00
parent 0f4f89edfe
commit 121f685fa2
1 changed files with 1 additions and 1 deletions
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src/fpu/fdivsqrt/fdivsqrtcycles.sv
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@ -76,7 +76,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
if (P.IDIV_ON_FPU) ResultBitsE = IntDivE ? IntResultBitsE : FPResultBitsE;
else ResultBitsE = FPResultBitsE;
assign CyclesE = (ResultBitsE-1)/(P.RK) + 1; // ceil (ResultBitsE/rk)
CyclesE = (ResultBitsE-1)/(P.RK) + 1; // ceil (ResultBitsE/rk)
end
/* verilator lint_on WIDTH */