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DTIM works without the store delay stall. Still a bit of work remaining. The DTIM needs cleanup.

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The cache needs a bit of clean up and the chapter needs updates.
The controller needs to be updated to remove the store delay hazard for cmo instructions.
This commit is contained in:
Rose Thompson 2023-12-13 20:32:14 -06:00
parent e089b421bb
commit b69a5b59cd
2 changed files with 23 additions and 8 deletions
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19
src/lsu/dtim.sv
View File

@ -28,14 +28,17 @@
////////////////////////////////////////////////////////////////////////////////////////////////
module dtim import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic clk, reset,
input logic FlushW,
input logic ce, // Chip Enable. 0: Holds ReadDataWordM
input logic [1:0] MemRWM, // Read/Write control
input logic [1:0] MemRWE, // Read/Write control
input logic [P.PA_BITS-1:0] DTIMAdr, // No stall: Execution stage memory address. Stall: Memory stage memory address
input logic [P.LLEN-1:0] WriteDataM, // Write data from IEU
input logic [P.LLEN/8-1:0] ByteMaskM, // Selects which bytes within a word to write
output logic [P.LLEN-1:0] ReadDataWordM // Read data before subword selection
output logic [P.LLEN-1:0] ReadDataWordM, // Read data before subword selection
output logic DTIMStall,
output logic DTIMSelWrite
);
logic we;
@ -47,8 +50,16 @@ module dtim import cvw::*; #(parameter cvw_t P) (
localparam ADDR_WDITH = $clog2(DEPTH);
localparam OFFSET = $clog2(LLENBYTES);
assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap.
logic DTIMStallHazard, DTIMStallHazardD;
assign DTIMStallHazard = MemRWM[0] & MemRWE[1];
flopr #(1) DTIMStallReg(clk, reset, DTIMStallHazard, DTIMStallHazardD);
assign DTIMStall = DTIMStallHazard & ~DTIMStallHazardD;
assign DTIMSelWrite = MemRWM[0] & ~(DTIMStallHazard & ~DTIMStall);
assign we = DTIMSelWrite & ~FlushW; // have to ignore write if Trap.
ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(DEPTH), .WIDTH(P.LLEN))
ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
ram(.clk, .ce(ce | DTIMSelWrite), .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
endmodule

12
src/lsu/lsu.sv
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@ -150,6 +150,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation
logic SelDTIM; // Select DTIM rather than bus or D$
logic [P.XLEN-1:0] WriteDataZM;
logic DTIMStall;
/////////////////////////////////////////////////////////////////////////////////////////////
// Pipeline for IEUAdr E to M
@ -219,7 +220,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
// the trap module.
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
assign GatedStallW = StallW & ~SelHPTW;
assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall;
assign CacheBusHPWTStall = DCacheStallM | HPTWStall | BusStall | DTIMStall;
assign LSUStallM = CacheBusHPWTStall | SpillStallM;
/////////////////////////////////////////////////////////////////////////////////////////////
@ -268,17 +269,20 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if (P.DTIM_SUPPORTED) begin : dtim
logic [P.PA_BITS-1:0] DTIMAdr;
logic [1:0] DTIMMemRWM;
logic DTIMSelWrite;
// The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], MemRWM[0], DTIMAdr);
mux2 #(P.PA_BITS) DTIMAdrMux(IEUAdrExtE[P.PA_BITS-1:0], IEUAdrExtM[P.PA_BITS-1:0], DTIMSelWrite, DTIMAdr);
assign DTIMMemRWM = SelDTIM & ~IgnoreRequestTLB ? LSURWM : '0;
// **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
// **** create config to support DTIM with floating point.
// Add support for cboz
dtim #(P) dtim(.clk, .ce(~GatedStallW), .MemRWM(DTIMMemRWM),
dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWE(MemRWE), // *** update when you update the cache RWE
.MemRWM(DTIMMemRWM),
.DTIMAdr, .FlushW, .WriteDataM(LSUWriteDataM),
.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM));
.ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM), .DTIMStall, .DTIMSelWrite);
end else begin
assign DTIMStall = '0;
end
if (P.BUS_SUPPORTED) begin : bus
if(P.DCACHE_SUPPORTED) begin : dcache