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https://github.com/openhwgroup/cvw
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Simplified integer postnormalization shift
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@ -67,7 +67,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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// Integer div/rem signals
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logic BZeroM; // Denominator is zero
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logic IntDivM; // Integer operation
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logic [P.DIVBLEN:0] mM, IntDivNormShiftM; // Shift amounts
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logic [P.DIVBLEN:0] IntNormShiftM; // Integer normalizatoin shift amount
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logic ALTBM, AsM, BsM, W64M; // Special handling for postprocessor
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logic [P.XLEN-1:0] AM; // Original Numerator for postprocessor
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logic ISpecialCaseE; // Integer div/remainder special cases
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@ -77,7 +77,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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.FmtE, .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE,
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// Int-specific
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.ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
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.BZeroM, .IntDivNormShiftM, .mM, .AM,
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.BZeroM, .IntNormShiftM, .AM,
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.IntDivM, .W64M, .ALTBM, .AsM, .BsM);
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fdivsqrtfsm #(P) fdivsqrtfsm( // FSM
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@ -96,6 +96,6 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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.SqrtE, .Firstun, .SqrtM, .SpecialCaseM,
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.UmM, .WZeroE, .DivStickyM,
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// Int-specific
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.IntDivNormShiftM, .mM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM,
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.IntNormShiftM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM,
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.FIntDivResultM);
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endmodule
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@ -37,7 +37,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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input logic Firstun, SqrtM, SpecialCaseM,
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input logic [P.XLEN-1:0] AM,
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input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
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input logic [P.DIVBLEN:0] mM, IntDivNormShiftM,
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input logic [P.DIVBLEN:0] IntNormShiftM,
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output logic [P.DIVb:0] UmM, // result significand
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output logic WZeroE,
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output logic DivStickyM,
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@ -96,7 +96,6 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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// Integer quotient or remainder correction, normalization, and special cases
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if (P.IDIV_ON_FPU) begin:intpostproc // Int supported
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logic [P.DIVBLEN:0] NormShiftM;
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logic [P.DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
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logic signed [P.DIVb+3:0] PreResultM, PreIntResultM;
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@ -110,10 +109,8 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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mux2 #(P.DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
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// Select quotient or remainder and do normalization shift
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localparam DIVa = (P.DIVb+1-P.XLEN); // used for idiv on fpu: Shift residual right by b - (XLEN-1) to put remainder in lsbs of integer result
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mux2 #(P.DIVBLEN+1) normshiftmux(IntDivNormShiftM, (mM + (P.DIVBLEN+1)'(DIVa)), RemOpM, NormShiftM);
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mux2 #(P.DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
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assign PreIntResultM = $signed(PreResultM >>> NormShiftM);
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assign PreIntResultM = $signed(PreResultM >>> IntNormShiftM);
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// special case logic
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// terminates immediately when B is Zero (div 0) or |A| has more leading 0s than |B|
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@ -42,7 +42,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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input logic IntDivE, W64E,
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output logic ISpecialCaseE,
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output logic [P.DURLEN-1:0] CyclesE,
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output logic [P.DIVBLEN:0] mM, IntDivNormShiftM,
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output logic [P.DIVBLEN:0] IntNormShiftM,
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output logic ALTBM, IntDivM, W64M,
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output logic AsM, BsM, BZeroM,
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output logic [P.XLEN-1:0] AM
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@ -193,10 +193,15 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .IntResultBits, .CyclesE);
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if (P.IDIV_ON_FPU) begin:intpipelineregs
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logic [P.DIVBLEN:0] IntDivNormShiftE;
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logic [P.DIVBLEN:0] IntDivNormShiftE, IntRemNormShiftE, IntNormShiftE;
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logic RemOpE;
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/* verilator lint_off WIDTH */
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assign IntDivNormShiftE = P.DIVb - (CyclesE * P.RK - P.LOGR); // b - rn, used for integer normalization right shift. rn = Cycles * r * k - r ***explain
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assign IntRemNormShiftE = mE + (P.DIVb+1-P.XLEN); // m + b - (N-1) for remainder normalization shift
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/* verilator lint_on WIDTH */
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assign RemOpE = Funct3E[1];
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mux2 #(P.DIVBLEN+1) normshiftmux(IntDivNormShiftE, IntRemNormShiftE, RemOpE, IntNormShiftE);
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// pipeline registers
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flopen #(1) mdureg(clk, IFDivStartE, IntDivE, IntDivM);
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@ -204,8 +209,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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flopen #(1) bzeroreg(clk, IFDivStartE, BZeroE, BZeroM);
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flopen #(1) asignreg(clk, IFDivStartE, AsE, AsM);
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flopen #(1) bsignreg(clk, IFDivStartE, BsE, BsM);
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flopen #(P.DIVBLEN+1) nsreg(clk, IFDivStartE, IntDivNormShiftE, IntDivNormShiftM);
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flopen #(P.DIVBLEN+1) mreg(clk, IFDivStartE, mE, mM);
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flopen #(P.DIVBLEN+1) nsreg(clk, IFDivStartE, IntNormShiftE, IntNormShiftM);
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flopen #(P.XLEN) srcareg(clk, IFDivStartE, AE, AM);
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if (P.XLEN==64)
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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