David Harris 6186181d46 Merge pull request #537 from ross144/main ... Almost having working Verilator. One issue in the testbench remains.		2023-12-18 18:13:56 -08:00
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cache	Added parameter for cache's SRAM length.	2023-12-18 12:50:49 -06:00
ebu	Extended the abhcacheinterface to zero a cacheline's worth of uncached memory on cbo.zero.	2023-11-27 21:24:30 -06:00
fpu	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
generic	Added parameter for cache's SRAM length.	2023-12-18 12:50:49 -06:00
hazard	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
ieu	Fixed the AMO hazard.	2023-12-15 11:55:54 -06:00
ifu	Merge branch 'main' of github.com:ross144/cvw	2023-12-13 20:32:59 -06:00
lsu	Fixed WALLY-lrsc in ImperasDV by setting reservation set size to native word size and adjusting imperas.ic lr_sc_grain=8 to match	2023-12-14 15:32:36 -08:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	Fixed issue 526 about WALLY-mmu-sv39-svadu-svnapot-svpbmt not checking ppn for NAPOT pages. Improved test case to check normal and malformed ppn	2023-12-13 19:43:17 -08:00
privileged	Renamed HADE to ADUE for Svadu	2023-12-13 11:49:04 -08:00
uncore	Simpilified pmachecker for cmo.	2023-11-29 12:26:18 -06:00
wally	Merge branch 'main' of github.com:ross144/cvw	2023-12-13 20:32:59 -06:00
cvw.sv	Added parameter for cache's SRAM length.	2023-12-18 12:50:49 -06:00