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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed bug. After I$ invalidated. If the pipelined wasn't stalled the I$ still output the old instruction on the next cycle. Now the I$ ensure that invalidation leads to the next cycle not hitting.
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5
src/cache/cacheway.sv
vendored
5
src/cache/cacheway.sv
vendored
@ -77,6 +77,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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logic ClearDirtyWay;
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logic SelNonHit;
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logic SelData;
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logic InvalidateCacheDelay;
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if (!READ_ONLY_CACHE) begin:flushlogic
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logic FlushWayEn;
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@ -121,7 +122,9 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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assign TagWay = SelData ? ReadTag : '0; // AND part of AOMux
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assign HitDirtyWay = Dirty & ValidWay;
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assign DirtyWay = SelDirty & HitDirtyWay;
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assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]);
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assign HitWay = ValidWay & (ReadTag == PAdr[PA_BITS-1:OFFSETLEN+INDEXLEN]) & ~InvalidateCacheDelay;
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flop #(1) InvalidateCacheReg(clk, InvalidateCache, InvalidateCacheDelay);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Data Array
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