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https://github.com/openhwgroup/cvw
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The misaligned load alignment lints.
This commit is contained in:
Rose Thompson
parent
834c0df697
commit
6041bf20b3
@ -36,7 +36,7 @@ module align import cvw::*; #(parameter cvw_t P) (
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input logic [P.XLEN-1:0] IEUAdrM, // 2 byte aligned PC in Fetch stage
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input logic [P.XLEN-1:0] IEUAdrE, // The next IEUAdrM
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input logic [2:0] Funct3M, // Size of memory operation
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input logic [31:0] ReadDataWordMuxM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
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input logic [P.LLEN*2-1:0]ReadDataWordMuxM, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
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input logic LSUStallM, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
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input logic DTLBMissM, // ITLB miss, ignore memory request
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input logic DataUpdateDAM, // ITLB miss, ignore memory request
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@ -44,7 +44,7 @@ module align import cvw::*; #(parameter cvw_t P) (
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output logic [P.XLEN-1:0] IEUAdrSpillE, // The next PCF for one of the two memory addresses of the spill
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output logic [P.XLEN-1:0] IEUAdrSpillM, // IEUAdrM for one of the two memory addresses of the spill
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output logic SelSpillE, // During the transition between the two spill operations, the IFU should stall the pipeline
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output logic [31:0] ReadDataWordSpillM)// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
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output logic [P.LLEN-1:0] ReadDataWordSpillM);// The final 32 bit instruction after merging the two spilled fetches into 1 instruction
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// Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1]
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typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
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@ -52,15 +52,17 @@ module align import cvw::*; #(parameter cvw_t P) (
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statetype CurrState, NextState;
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logic TakeSpillM, TakeSpillE;
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logic SpillM;
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logic SelSpillF;
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logic SpillSaveF;
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logic [LLEN-8:0] ReadDataWordFirstHalfM;
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logic SelSpillM;
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logic SpillSaveM;
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logic [P.LLEN-1:0] ReadDataWordFirstHalfM;
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logic MisalignedM;
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logic [P.LLEN*2-1:0] ReadDataWordSpillAllM;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// PC logic
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////////////////////////////////////////////////////////////////////////////////////////////////////
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localparam LLENINBYTES = LLEN/8;
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localparam LLENINBYTES = P.LLEN/8;
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logic IEUAdrIncrementM;
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assign IEUAdrIncrementM = IEUAdrM + LLENINBYTES;
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mux2 #(P.XLEN) pcplus2mux(.d0({IEUAdrM[P.XLEN-1:2], 2'b10}), .d1(IEUAdrIncrementM), .s(TakeSpillM), .y(IEUAdrSpillM));
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@ -110,18 +112,30 @@ module align import cvw::*; #(parameter cvw_t P) (
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assign SpillSaveM = (CurrState == STATE_READY) & TakeSpillM & ~FlushM;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Merge spilled instruction
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// Merge spilled data
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// save the first 2 bytes
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flopenr #(P.LLEN-8) SpillDataReg(clk, reset, SpillSaveM, ReadDataWordMuxM[LLEN-1:8], ReadDataWordFirstHalfM);
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flopenr #(P.LLEN) SpillDataReg(clk, reset, SpillSaveM, ReadDataWordMuxM[P.LLEN-1:0], ReadDataWordFirstHalfM);
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// merge together
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mux2 #(32) postspillmux(InstrRawF, {InstrRawF[15:0], InstrFirstHalfF}, SpillF, PostSpillInstrRawF);
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mux2 #(2*P.LLEN) postspillmux(ReadDataWordMuxM, {ReadDataWordMuxM[P.LLEN-1:0], ReadDataWordFirstHalfM}, SpillM, ReadDataWordSpillAllM);
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// Need to use always comb to avoid pessimistic x propagation if PostSpillInstrRawF is x
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always_comb
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if (PostSpillInstrRawF[1:0] != 2'b11) CompressedF = 1'b1;
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else CompressedF = 1'b0;
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// align by shifting
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// *** optimize by merging with halfSpill, WordSpill, etc
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logic HalfMisalignedM, WordMisalignedM;
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assign HalfMisalignedM = Funct3M[1:0] == 2'b01 & ByteOffsetM[0] != 1'b0;
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assign WordMisalignedM = Funct3M[1:0] == 2'b10 & ByteOffsetM[1:0] != 2'b00;
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if(P.LLEN == 64) begin
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logic DoubleMisalignedM;
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assign DoubleMisalignedM = Funct3M[1:0] == 2'b11 & ByteOffsetM[2:0] != 3'b00;
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assign MisalignedM = HalfMisalignedM | WordMisalignedM | DoubleMisalignedM;
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end else begin
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assign MisalignedM = HalfMisalignedM | WordMisalignedM;
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end
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// shifter (4:1 mux for 32 bit, 8:1 mux for 64 bit)
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// 8 * is for shifting by bytes not bits
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assign ReadDataWordSpillM = ReadDataWordSpillAllM >> (MisalignedM ? 8 * ByteOffsetM : '0);
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endmodule
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@ -1,249 +0,0 @@
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///////////////////////////////////////////
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// subwordread.sv
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//
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// Written: David_Harris@hmc.edu
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// Created: 9 January 2021
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// Modified: 18 January 2023
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//
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// Purpose: Extract subwords and sign extend for reads
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module subwordreadVar1 #(parameter LLEN)
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(
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input logic [LLEN-1:0] ReadDataWordMuxM,
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input logic [$clog(LLEN/8)-1:0] PAdrM,
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input logic [2:0] Funct3M,
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input logic FpLoadStoreM,
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input logic BigEndianM,
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output logic [LLEN/2-1:0] ReadDataM
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);
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localparam OFFSET_LEN = $clog(LLEN/8);
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localparam HLEN = LLEN/2;
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logic [7:0] ByteM;
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logic [15:0] HalfwordM;
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logic [OFFSET_LEN-1:0] PAdrSwap;
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// Funct3M[2] is the unsigned bit. mask upper bits.
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// Funct3M[1:0] is the size of the memory access.
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assign PAdrSwap = PAdrM ^ {OFFSET_LEN{BigEndianM}};
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if (LLEN == 128) begin:swrmux
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// ByteMe mux
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: ByteM = ReadDataWordMuxM[7:0];
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4'b0001: ByteM = ReadDataWordMuxM[15:8];
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4'b0010: ByteM = ReadDataWordMuxM[23:16];
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4'b0011: ByteM = ReadDataWordMuxM[31:24];
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4'b0100: ByteM = ReadDataWordMuxM[39:32];
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4'b0101: ByteM = ReadDataWordMuxM[47:40];
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4'b0110: ByteM = ReadDataWordMuxM[55:48];
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4'b0111: ByteM = ReadDataWordMuxM[63:56];
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4'b1000: ByteM = ReadDataWordMuxM[71:64];
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4'b1001: ByteM = ReadDataWordMuxM[79:72];
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4'b1010: ByteM = ReadDataWordMuxM[87:80];
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4'b1011: ByteM = ReadDataWordMuxM[95:88];
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4'b1100: ByteM = ReadDataWordMuxM[103:96];
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4'b1101: ByteM = ReadDataWordMuxM[111:104];
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4'b1110: ByteM = ReadDataWordMuxM[119:112];
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4'b1111: ByteM = ReadDataWordMuxM[127:120];
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endcase
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// halfword mux
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: HalfwordM = ReadDataWordMuxM[15:0];
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4'b0001: HalfwordM = ReadDataWordMuxM[23:8];
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4'b0010: HalfwordM = ReadDataWordMuxM[31:16];
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4'b0011: HalfwordM = ReadDataWordMuxM[39:24];
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4'b0100: HalfwordM = ReadDataWordMuxM[47:32];
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4'b0101: HalfwordM = ReadDataWordMuxM[55:40];
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4'b0110: HalfwordM = ReadDataWordMuxM[63:48];
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4'b0111: HalfwordM = ReadDataWordMuxM[71:56];
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4'b1000: HalfwordM = ReadDataWordMuxM[79:64];
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4'b1001: HalfwordM = ReadDataWordMuxM[87:72];
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4'b1010: HalfwordM = ReadDataWordMuxM[95:80];
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4'b1011: HalfwordM = ReadDataWordMuxM[103:88];
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4'b1100: HalfwordM = ReadDataWordMuxM[111:96];
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4'b1101: HalfwordM = ReadDataWordMuxM[119:104];
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4'b1110: HalfwordM = ReadDataWordMuxM[127:112];
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//4'b1111: HalfwordM = {ReadDataWordMuxM[7:0], ReadDataWordMuxM[127:120]}; // *** might be ok to zero extend rather than wrap around
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4'b1111: HalfwordM = {8'b0, ReadDataWordMuxM[127:120]}; // *** might be ok to zero extend rather than wrap around
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endcase
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logic [31:0] WordM;
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: WordM = ReadDataWordMuxM[31:0];
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4'b0001: WordM = ReadDataWordMuxM[39:8];
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4'b0010: WordM = ReadDataWordMuxM[47:16];
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4'b0011: WordM = ReadDataWordMuxM[55:24];
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4'b0100: WordM = ReadDataWordMuxM[63:32];
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4'b0101: WordM = ReadDataWordMuxM[71:40];
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4'b0111: WordM = ReadDataWordMuxM[79:48];
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4'b1000: WordM = ReadDataWordMuxM[87:56];
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4'b1001: WordM = ReadDataWordMuxM[95:64];
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4'b1010: WordM = ReadDataWordMuxM[103:72];
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4'b1011: WordM = ReadDataWordMuxM[111:80];
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4'b1011: WordM = ReadDataWordMuxM[119:88];
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4'b1100: WordM = ReadDataWordMuxM[127:96];
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4'b1101: WordM = {8'b0, ReadDataWordMuxM[127:104]};
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4'b1110: WordM = {16'b0, ReadDataWordMuxM[127:112]};
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4'b1111: WordM = {24'b0, ReadDataWordMuxM[127:120]};
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endcase
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logic [63:0] DblWordM;
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always_comb
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case(PAdrSwap[3:0])
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4'b0000: DblWordMM = ReadDataWordMuxM[63:0];
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4'b0001: DblWordMM = ReadDataWordMuxM[71:8];
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4'b0010: DblWordMM = ReadDataWordMuxM[79:16];
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4'b0011: DblWordMM = ReadDataWordMuxM[87:24];
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4'b0100: DblWordMM = ReadDataWordMuxM[95:32];
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4'b0101: DblWordMM = ReadDataWordMuxM[103:40];
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4'b0111: DblWordMM = ReadDataWordMuxM[111:48];
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4'b1000: DblWordMM = ReadDataWordMuxM[119:56];
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4'b1001: DblWordMM = ReadDataWordMuxM[127:64];
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4'b1010: DblWordMM = {8'b0, ReadDataWordMuxM[103:72]};
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4'b1011: DblWordMM = {16'b0, ReadDataWordMuxM[111:80]};
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4'b1011: DblWordMM = {24'b0, ReadDataWordMuxM[119:88]};
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4'b1100: DblWordMM = {32'b0, ReadDataWordMuxM[127:96]};
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4'b1101: DblWordMM = {40'b0, ReadDataWordMuxM[127:104]};
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4'b1110: DblWordMM = {48'b0, ReadDataWordMuxM[127:112]};
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4'b1111: DblWordMM = {56'b0, ReadDataWordMuxM[127:120]};
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endcase
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// sign extension/ NaN boxing
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{HLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{HLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{HLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b011: ReadDataM = {{HLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
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3'b100: ReadDataM = {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
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3'b101: ReadDataM = {{HLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b110: ReadDataM = {{HLEN-32{1'b0}}, WordM[31:0]}; // lwu
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default: ReadDataM = ReadDataWordMuxM[HLEN-1:0]; // Shouldn't happen
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endcase
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end else if (LLEN == 64) begin:swrmux
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// ByteMe mux
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always_comb
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case(PAdrSwap[2:0])
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3'b000: ByteM = ReadDataWordMuxM[7:0];
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3'b001: ByteM = ReadDataWordMuxM[15:8];
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3'b010: ByteM = ReadDataWordMuxM[23:16];
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3'b011: ByteM = ReadDataWordMuxM[31:24];
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3'b100: ByteM = ReadDataWordMuxM[39:32];
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3'b101: ByteM = ReadDataWordMuxM[47:40];
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3'b110: ByteM = ReadDataWordMuxM[55:48];
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3'b111: ByteM = ReadDataWordMuxM[63:56];
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endcase
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// halfword mux
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always_comb
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case(PAdrSwap[2:0])
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3'b000: HalfwordM = ReadDataWordMuxM[15:0];
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3'b001: HalfwordM = ReadDataWordMuxM[23:8];
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3'b010: HalfwordM = ReadDataWordMuxM[31:16];
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3'b011: HalfwordM = ReadDataWordMuxM[39:24];
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3'b100: HalfwordM = ReadDataWordMuxM[47:32];
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3'b011: HalfwordM = ReadDataWordMuxM[55:40];
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3'b110: HalfwordM = ReadDataWordMuxM[63:48];
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3'b011: HalfwordM = {8'b0, ReadDataWordMuxM[63:56]};
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endcase
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logic [31:0] WordM;
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always_comb
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case(PAdrSwap[2:0])
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3'b000: WordM = ReadDataWordMuxM[31:0];
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3'b001: WordM = ReadDataWordMuxM[39:8];
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3'b010: WordM = ReadDataWordMuxM[47:16];
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3'b011: WordM = ReadDataWordMuxM[55:24];
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3'b100: WordM = ReadDataWordMuxM[63:32];
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3'b101: WordM = {8'b0, ReadDataWordMuxM[63:40]};
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3'b110: WordM = {16'b0, ReadDataWordMuxM[63:48]};
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3'b111: WordM = {24'b0, ReadDataWordMuxM[63:56]};
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endcase
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logic [63:0] DblWordM;
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always_comb
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case(PAdrSwap[2:0])
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3'b000: DblWordMM = ReadDataWordMuxM[63:0];
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3'b001: DblWordMM = {8'b0, ReadDataWordMuxM[63:8]};
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3'b010: DblWordMM = {16'b0, ReadDataWordMuxM[63:16]};
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3'b011: DblWordMM = {24'b0, ReadDataWordMuxM[63:24]};
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3'b100: DblWordMM = {32'b0, ReadDataWordMuxM[63:32]};
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3'b101: DblWordMM = {40'b0, ReadDataWordMuxM[63:40]};
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3'b110: DblWordMM = {48'b0, ReadDataWordMuxM[63:48]};
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3'b111: DblWordMM = {56'b0, ReadDataWordMuxM[63:56]};
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endcase
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// sign extension/ NaN boxing
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{HLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{HLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{HLEN-32{WordM[31]|FpLoadStoreM}}, WordM[31:0]}; // lw/flw
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3'b011: ReadDataM = {{HLEN-64{DblWordM[63]|FpLoadStoreM}}, DblWordM[63:0]}; // ld/fld
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3'b100: ReadDataM = {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu
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//3'b100: ReadDataM = FpLoadStoreM ? ReadDataWordMuxM : {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu/flq - only needed when LLEN=128
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3'b101: ReadDataM = {{HLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
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3'b110: ReadDataM = {{HLEN-32{1'b0}}, WordM[31:0]}; // lwu
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default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
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endcase
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end else begin:swrmux // 32-bit
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// byte mux
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always_comb
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case(PAdrSwap[1:0])
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2'b00: ByteM = ReadDataWordMuxM[7:0];
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2'b01: ByteM = ReadDataWordMuxM[15:8];
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2'b10: ByteM = ReadDataWordMuxM[23:16];
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2'b11: ByteM = ReadDataWordMuxM[31:24];
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endcase
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// halfword mux
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always_comb
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case(PAdrSwap[1:0])
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2'b00: HalfwordM = ReadDataWordMuxM[15:0];
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2'b01: HalfwordM = ReadDataWordMuxM[23:8];
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2'b10: HalfwordM = ReadDataWordMuxM[31:16];
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2'b11: HalfwordM = {8'b0, ReadDataWordMuxM[31:24]};
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endcase
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// sign extension
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always_comb
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case(Funct3M)
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3'b000: ReadDataM = {{HLEN-8{ByteM[7]}}, ByteM}; // lb
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3'b001: ReadDataM = {{HLEN-16{HalfwordM[15]|FpLoadStoreM}}, HalfwordM[15:0]}; // lh/flh
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3'b010: ReadDataM = {{HLEN-32{ReadDataWordMuxM[31]|FpLoadStoreM}}, ReadDataWordMuxM[31:0]}; // lw/flw
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3'b011: ReadDataM = ReadDataWordMuxM; // fld
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3'b100: ReadDataM = {{HLEN-8{1'b0}}, ByteM[7:0]}; // lbu
|
||||
3'b101: ReadDataM = {{HLEN-16{1'b0}}, HalfwordM[15:0]}; // lhu
|
||||
default: ReadDataM = ReadDataWordMuxM; // Shouldn't happen
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
@ -264,7 +264,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
end
|
||||
|
||||
// global stall and flush control
|
||||
hazard hzu(.clk, .reset,
|
||||
hazard hzu(
|
||||
.BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
|
||||
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
|
||||
.LSUStallM, .IFUStallF,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user