Merge branch 'main' into spi

.gitattributes

@@ -1 +0,0 @@
-pipelined/busybear_boot/* filter=lfs diff=lfs merge=lfs -text

.gitignore

@@ -83,7 +83,6 @@ synthDC/ppa/plots
 synthDC/wallyplots/
 synthDC/runArchive
 synthDC/hdl
-synthDC/wrappers
 sim/power.saif
 tests/fp/vectors/*.tv
 synthDC/Summary.csv

src/generic/mem/ram1p1rwbe.sv

@@ -90,12 +90,12 @@ module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=
       end
     end
     
-    // Read
+    // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
     flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
     assign dout = RAM[addrd];
 
-    /*      // Read
+    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
      always_ff @(posedge clk) 
      if(ce) dout <= #1 mem[addr]; */
 

src/generic/mem/ram1p1rwe.sv

@@ -71,12 +71,12 @@ module ram1p1rwe import cvw::* ; #(parameter cvw_t P,
     // The version with byte write enables it correctly infers block ram.
     integer i;
 
-    // Read
+    // Combinational read: register address and read after clock edge
     logic [$clog2(DEPTH)-1:0] addrd;
     flopen #($clog2(DEPTH)) adrreg(clk, ce, addr, addrd);
     assign dout = RAM[addrd];
 
-    /*      // Read
+    /*      // Alternate read logic reads the old contents of mem[addr].  Increases setup time and adds dout reg, but reduces clk to q
      always_ff @(posedge clk) 
      if(ce) dout <= #1 mem[addr]; */
 

src/generic/mem/rom1p1r.sv

@@ -36,6 +36,9 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
 
    // Core Memory
    logic [DATA_WIDTH-1:0]    ROM [(2**ADDR_WIDTH)-1:0];
+   
+   // dh 10/30/23 ROM macros are presently commented out
+   // because they don't point to a generated ROM
 /*   if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 64)) begin
       rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));
 
@@ -43,9 +46,9 @@ module rom1p1r #(parameter ADDR_WIDTH = 8,
       rom1p1r_128x32 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout));      
 
    end else begin */
-   always @ (posedge clk) begin
-   if(ce) dout <= ROM[addr];    
-   end
+   always @ (posedge clk) 
+      if(ce) dout <= ROM[addr];    
+   
    
    // for FPGA, initialize with zero-stage bootloader
    if(PRELOAD_ENABLED) begin

src/ifu/ifu.sv

@@ -389,24 +389,31 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.COMPRESSED_SUPPORTED) & PCSrcE;
   flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
-  // Instruction and PC/PCLink pipeline registers
+  // Instruction and PC pipeline registers
   // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.
   mux2    #(32)     FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
   mux2    #(32)     FlushInstrMMux(InstrE, nop, FlushM, NextInstrE);
   flopenr #(32)     InstrEReg(clk, reset, ~StallE, NextInstrD, InstrE);
-  flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
   flopenr #(P.XLEN) PCEReg(clk, reset, ~StallE, PCD, PCE);
-  flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
-  //flopenr #(P.XLEN) PCPDReg(clk, reset, ~StallD, PCPlus2or4F, PCLinkD);
-  //flopenr #(P.XLEN) PCPEReg(clk, reset, ~StallE, PCLinkD, PCLinkE);
+
+  // InstrM is only needed with CSRs or atomic operations
+  if (P.ZICSR_SUPPORTED | P.A_SUPPORTED)
+    flopenr #(32)     InstrMReg(clk, reset, ~StallM, NextInstrE, InstrM);
+  else assign InstrM = 0;
+  // PCM is only needed with CSRs or branch prediction
+  if (P.ZICSR_SUPPORTED | P.BPRED_SUPPORTED) 
+    flopenr #(P.XLEN) PCMReg(clk, reset, ~StallM, PCE, PCM);
+  else assign PCM = 0;
 
   flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
   flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
   assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion
 
   // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
-  flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
-  flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
-  flopenrc #(1)  CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
-  mux2     #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM); 
+  if (P.ZICSR_SUPPORTED) begin
+    flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
+    flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
+    flopenrc #(1)  CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM);
+    mux2     #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM); 
+  end else assign InstrOrigM = 0;
 endmodule

src/ifu/irom.sv

@@ -37,17 +37,21 @@ module irom import cvw::*;  #(parameter cvw_t P) (
 
   logic [P.XLEN-1:0] IROMInstrFFull;
   logic [31:0]       RawIROMInstrF;
-  logic [1:0]        AdrD;
-  flopen #(2) AdrReg(clk, ce, Adr[2:1], AdrD);
+  logic [2:1]        AdrD;
 
   rom1p1r #(ADDR_WDITH, P.XLEN) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(IROMInstrFFull));
   if (P.XLEN == 32) assign RawIROMInstrF = IROMInstrFFull;
   else              begin
   // IROM is aligned to XLEN words, but instructions are 32 bits.  Select between the two
   // haves.  Adr is the Next PCF not PCF so we delay 1 cycle.
-    assign RawIROMInstrF = AdrD[1] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
+    flopen #(1) AdrReg2(clk, ce, Adr[2], AdrD[2]);
+    assign RawIROMInstrF = AdrD[2] ? IROMInstrFFull[63:32] : IROMInstrFFull[31:0];
   end
   // If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
   // The spill logic will handle merging the two together.
-  assign IROMInstrF = AdrD[0] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
+  if (P.COMPRESSED_SUPPORTED) begin
+    flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]);
+    assign IROMInstrF = AdrD[1] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
+  end else
+    assign IROMInstrF = RawIROMInstrF;
 endmodule  

synthDC/Makefile

@@ -147,4 +147,4 @@ clean:
 	rm -f power.saif
 	rm -f Synopsys_stack_trace_*.txt
 	rm -f crte_*.txt
-	rm $(WALLY)/synthDC/wrappers/*
+	

synthDC/extractArea.pl

@@ -96,10 +96,11 @@ sub processRun {
         foreach my $kw (@keywords) {
            # print "$kw $line\n";
             if ($line =~ /^${kw}\s+(\S*)/) {
-                #print "$line $kw $1\n";
+                $results{$kw} = int($1);
+            } elsif ($line =~ /^${kw}__\S*\s+(\S*)/) {
                 $results{$kw} = int($1);
             }
-        }
+         }
     }
     foreach my $kw (@keywords) {
         #print "$kw\t$results{$kw}\n";

synthDC/extractSummary.py

@@ -149,9 +149,10 @@ def areaDelay(tech, delays, areas, labels, fig, ax, norm=False):
     plt.ylim(ymin=0, ymax=1.1*ytop)
     
     ax.yaxis.set_major_formatter(ticker.StrMethodFormatter('{x:,.0f}'))
-
-    texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))]
-    adjust_text(texts)
+    
+    if (len(labels) > 0):
+        texts = [plt.text(delays[i], areas[i], labels[i], ha='center', va='center') for i in range(len(labels))]
+        adjust_text(texts)
     return fig
 
 
@@ -166,7 +167,7 @@ def plotFeatures(tech, width, config):
                 labels += [oneSynth.mod]
 
     if (delays == []):
-        print("No delays found for freq ", freq, ". Did you set --skyfreq and --tsmcfreq?\n")
+        print("No delays found for tech ", tech, " freq ", freq, ". Did you set --sky130freq, --sky90freq and --tsmcfreq?\n")
 
     fig, (ax) = plt.subplots(1, 1)
 
@@ -244,13 +245,15 @@ def addFO4axis(fig, ax, tech):
 if __name__ == '__main__':
 
     parser = argparse.ArgumentParser()
-    parser.add_argument("-s", "--skyfreq", type=int, default=1500, help = "Target frequency used for sky90 syntheses")
+    parser.add_argument("-s130", "--sky130freq", type=int, default=500, help = "Target frequency used for sky130 syntheses")
+    parser.add_argument("-s90", "--sky90freq", type=int, default=1500, help = "Target frequency used for sky90 syntheses")
     parser.add_argument("-t", "--tsmcfreq", type=int, default=5000, help = "Target frequency used for tsmc28 syntheses")
     args = parser.parse_args()
 
     TechSpec = namedtuple("TechSpec", "color shape targfreq fo4 add32area add32lpower add32denergy")
     techdict = {}
-    techdict['sky90'] = TechSpec('gray', 'o', args.skyfreq, 43.2e-3, 1440.600027, 714.057, 0.658023)
+    techdict['sky130'] = TechSpec('green', 'o', args.sky130freq, 99.5e-3, 1440.600027, 714.057, 0.658023)
+    techdict['sky90'] = TechSpec('gray', 'o', args.sky90freq, 43.2e-3, 1440.600027, 714.057, 0.658023)
     techdict['tsmc28psyn'] = TechSpec('blue', 's', args.tsmcfreq, 12.2e-3, 209.286002, 1060.0, .081533)
 
     current_directory = os.getcwd()
@@ -262,9 +265,12 @@ if __name__ == '__main__':
     synthsfromcsv('Summary.csv')
     freqPlot('tsmc28psyn', 'rv32', 'e')
     freqPlot('sky90', 'rv32', 'e')
+    freqPlot('sky130', 'rv32', 'e')
     plotFeatures('sky90', 'rv64', 'gc')
+    plotFeatures('sky130', 'rv64', 'gc')
     plotFeatures('tsmc28psyn', 'rv64', 'gc')
     plotConfigs('sky90', mod='orig')
+    plotConfigs('sky130', mod='orig')
     plotConfigs('tsmc28psyn', mod='orig')
     normAreaDelay(mod='orig')
     os.system("./extractArea.pl");

synthDC/scripts/synth.tcl

@@ -36,8 +36,8 @@ eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/}
 set wrapper 0
 if {[eval exec grep "cvw_t" {$outputDir/hdl/$::env(DESIGN).sv}] ne ""} {
     set wrapper 1
-	exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN)
-    eval file copy -force [glob ${hdl_src}/../synthDC/wrappers/$::env(DESIGN)wrapper.sv] {$outputDir/hdl/}
+    # make the wrapper
+	exec python3 $::env(WALLY)/synthDC/scripts/wrapperGen.py $::env(DESIGN) $outputDir/hdl
 }
 
 # Only for FMA class project; comment out when done

synthDC/scripts/wrapperGen.py

@@ -15,6 +15,7 @@ import os
 parser = argparse.ArgumentParser()
 
 parser.add_argument("DESIGN")
+parser.add_argument("HDLPATH");
 
 args=parser.parse_args()
 
@@ -60,11 +61,7 @@ for l in lines:
 buf += f"\t{moduleName} #(P) dut(.*);\nendmodule"
 
 # path to wrapper
-wrapperPath = f"{os.getenv('WALLY')}/synthDC/wrappers/{moduleName}wrapper.sv"
-
-# clear wrappers directory 
-os.system(f"rm -f {os.getenv('WALLY')}/synthDC/wrappers/*")
-os.system(f"mkdir -p {os.getenv('WALLY')}/synthDC/wrappers")
+wrapperPath = f"{args.HDLPATH}/{moduleName}wrapper.sv"
 
 fout = open(wrapperPath, "w")
 
@@ -73,6 +70,4 @@ fout.write(buf)
 fin.close()
 fout.close()
 
-
-
 #print(buf)

synthDC/wallySynth.py

@@ -16,7 +16,7 @@ def mask(command):
 
 if __name__ == '__main__':
     
-    techs = ['sky90', 'tsmc28', 'tsmc28psyn']
+    techs = ['sky130', 'sky90', 'tsmc28', 'tsmc28psyn']
     allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i']
     freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20]
 #    freqVaryPct = [-20, -10, 0, 10, 20]