cvw/src
2024-01-15 07:16:11 -08:00
..
cache Cleanup. 2023-12-29 16:18:30 -06:00
ebu Found bugs in the no I$ implementation's abhinterface width. We were only testing XLEN=32. XLEN=64 did not properly align instructions not aligned to 8 byte boundaries. 2024-01-06 22:29:16 -06:00
fpu Corrected spelling of negative 2024-01-15 07:15:23 -08:00
generic Revert RAM logic to bit change. 2023-12-20 13:10:20 -06:00
hazard Moved forwarding logic into controller 2023-12-26 21:17:01 -08:00
ieu Cleaned up Zicond implementation 2024-01-12 18:12:52 -08:00
ifu correct c.sext.b encoding and remove unreachable code in 01100 case 2024-01-12 19:09:10 -08:00
lsu Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
mdu turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
mmu Fixed typo in declaration in tlbcontrol; escape quoted argument to Verilator; added ulimit to setup so Verilator stack is large enough 2024-01-06 07:11:25 -08:00
privileged tests/coverage/tlbmisc.S 2024-01-15 07:16:11 -08:00
uncore Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match 2023-12-21 12:29:37 -08:00
wally Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
cvw.sv Added Zicond support 2024-01-11 07:37:15 -08:00