Rose Thompson fbab9f6c6d Updated comments about AMO and CMO stalls.		2023-12-29 15:31:11 -06:00
..
cache	Renamed CMOp to CMOpM in mmu and cache	2023-12-25 05:57:41 -08:00
ebu	Added partial code for uncached amo operations.	2023-12-29 15:07:20 -06:00
fpu	Removed other unused signals from Verilog	2023-11-20 23:37:56 -08:00
generic	Revert RAM logic to bit change.	2023-12-20 13:10:20 -06:00
hazard	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
ieu	Updated comments about AMO and CMO stalls.	2023-12-29 15:31:11 -06:00
ifu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-12-29 15:13:18 -06:00
lsu	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-12-29 15:13:18 -06:00
mdu	turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep	2023-11-17 20:25:24 -08:00
mmu	fixed coverage exclusions in lsu and ifu	2023-12-29 11:18:23 -08:00
privileged	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
uncore	Reversed numbering of adrdecs to make it easier to add new peripherals without renumbering the old ones; update figure to match	2023-12-21 12:29:37 -08:00
wally	Moved forwarding logic into controller	2023-12-26 21:17:01 -08:00
cvw.sv	Added parameter for cache's SRAM length.	2023-12-18 12:50:49 -06:00