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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Divsqrt cleanup: change Q to U, commenting code
This commit is contained in:
David Harris
parent
953c53d065
commit
255873a50c
@ -45,8 +45,8 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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input logic IntDivE, W64E,
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output logic DivStickyM,
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output logic FDivBusyE, IFDivStartE, FDivDoneE,
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output logic [P.NE+1:0] QeM,
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output logic [P.DIVb:0] QmM,
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output logic [P.NE+1:0] UeM, // Exponent result
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output logic [P.DIVb:0] UmM, // Significand result
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output logic [P.XLEN-1:0] FIntDivResultM
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);
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@ -74,7 +74,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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fdivsqrtpreproc #(P) fdivsqrtpreproc( // Preprocessor
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.clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
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.FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .CyclesE,
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.FmtE, .SqrtE, .XZeroE, .Funct3E, .UeM, .X, .D, .CyclesE,
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// Int-specific
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.ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
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.BZeroM, .nM, .mM, .AM,
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@ -94,7 +94,7 @@ module fdivsqrt import cvw::*; #(parameter cvw_t P) (
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fdivsqrtpostproc #(P) fdivsqrtpostproc( // Postprocessor
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.clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC,
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.SqrtE, .Firstun, .SqrtM, .SpecialCaseM,
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.QmM, .WZeroE, .DivStickyM,
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.UmM, .WZeroE, .DivStickyM,
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// Int-specific
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.nM, .mM, .ALTBM, .AsM, .BsM, .BZeroM, .W64M, .RemOpM(Funct3M[1]), .AM,
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.FIntDivResultM);
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@ -68,7 +68,7 @@ module fdivsqrtcycles import cvw::*; #(parameter cvw_t P) (
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if (SqrtE) fbits = Nf + 2 + 1; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2 *** unclear why it works with just +1; is it related to DIVCOPIES logic below?
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// if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
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else fbits = Nf + 2 + P.LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
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if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
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if (P.IDIV_ON_FPU) CyclesE = IntDivE ? ((nE + 1)/P.DIVCOPIES) : (fbits -1)/(P.RK) + 1;
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else CyclesE = (fbits + (P.LOGR*P.DIVCOPIES)-1)/(P.LOGR*P.DIVCOPIES);
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end
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/* verilator lint_on WIDTH */
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@ -32,8 +32,9 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
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input logic Sqrt,
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input logic XZero,
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input logic [P.DIVBLEN:0] ell, m,
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output logic [P.NE+1:0] Qe
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output logic [P.NE+1:0] Ue
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);
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logic [P.NE-2:0] Bias;
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logic [P.NE+1:0] SXExp;
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logic [P.NE+1:0] SExp;
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@ -63,10 +64,14 @@ module fdivsqrtexpcalc import cvw::*; #(parameter cvw_t P) (
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2'h2: Bias = (P.NE-1)'(P.H_BIAS);
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endcase
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end
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// Square root exponent = (Xe - l - bias) / 2 + bias; l accounts for subnorms
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assign SXExp = {2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - (P.NE+2)'(P.BIAS);
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assign SExp = {SXExp[P.NE+1], SXExp[P.NE+1:1]} + {2'b0, Bias};
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// correct exponent for subnormal input's normalization shifts
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// division exponent = (Xe-l) - (Ye-m) + bias; l and m account for subnorms
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assign DExp = ({2'b0, Xe} - {{(P.NE+1-P.DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(P.NE+1-P.DIVBLEN){1'b0}}, m} + {3'b0, Bias});
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assign Qe = Sqrt ? SExp : DExp;
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// Select square root or division exponent
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assign Ue = Sqrt ? SExp : DExp;
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endmodule
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@ -38,14 +38,14 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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input logic [P.XLEN-1:0] AM,
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input logic RemOpM, ALTBM, BZeroM, AsM, BsM, W64M,
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input logic [P.DIVBLEN:0] nM, mM,
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output logic [P.DIVb:0] QmM,
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output logic [P.DIVb:0] UmM, // result significand
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output logic WZeroE,
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output logic DivStickyM,
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output logic [P.XLEN-1:0] FIntDivResultM
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);
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logic [P.DIVb+3:0] W, Sum;
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logic [P.DIVb:0] PreQmM;
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logic [P.DIVb:0] PreUmM;
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logic NegStickyM;
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logic weq0E, WZeroM;
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logic [P.XLEN-1:0] IntDivResultM;
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@ -91,17 +91,17 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
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// Determine if sticky bit is negative // *** look for ways to optimize this. Shift shouldn't be needed.
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assign Sum = WC + WS;
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assign NegStickyM = Sum[P.DIVb+3];
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mux2 #(P.DIVb+1) preqmmux(FirstU, FirstUM, NegStickyM, PreQmM); // Select U or U-1 depending on negative sticky bit
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mux2 #(P.DIVb+1) qmmux(PreQmM, (PreQmM << 1), SqrtM, QmM);
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mux2 #(P.DIVb+1) preummux(FirstU, FirstUM, NegStickyM, PreUmM); // Select U or U-1 depending on negative sticky bit
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mux2 #(P.DIVb+1) ummux(PreUmM, (PreUmM << 1), SqrtM, UmM);
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// Integer quotient or remainder correctoin, normalization, and special cases
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// Integer quotient or remainder correction, normalization, and special cases
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if (P.IDIV_ON_FPU) begin:intpostproc // Int supported
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logic [P.DIVBLEN:0] NormShiftM;
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logic [P.DIVb+3:0] UnsignedQuotM, NormRemM, NormRemDM, NormQuotM;
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logic signed [P.DIVb+3:0] PreResultM, PreIntResultM;
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assign W = $signed(Sum) >>> P.LOGR;
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assign UnsignedQuotM = {3'b000, PreQmM};
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assign UnsignedQuotM = {3'b000, PreUmM};
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// Integer remainder: sticky and sign correction muxes
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assign NegQuotM = AsM ^ BsM; // Integer Quotient is negative
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@ -35,7 +35,7 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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input logic SqrtE,
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input logic XZeroE,
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input logic [2:0] Funct3E,
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output logic [P.NE+1:0] QeM,
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output logic [P.NE+1:0] UeM,
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output logic [P.DIVb+3:0] X, D,
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// Int-specific
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input logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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@ -48,10 +48,10 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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output logic [P.XLEN-1:0] AM
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);
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logic [P.DIVb:0] Xfract, Dfract;
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logic [P.DIVb:0] Xnorm, Dnorm;
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logic [P.DIVb:0] PreSqrtX;
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logic [P.DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
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logic [P.NE+1:0] QeE; // Quotient Exponent (FP only)
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logic [P.NE+1:0] UeE; // Result Exponent (FP only)
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logic [P.DIVb:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
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logic [P.DIVBLEN:0] mE, nE, ell; // Leading zeros of inputs
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logic NumerZeroE; // Numerator is zero (X or A)
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@ -106,9 +106,9 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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lzc #(P.DIVb+1) lzcX (IFX, ell);
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lzc #(P.DIVb+1) lzcY (IFD, mE);
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// Normalization shift: shift off leading one
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assign Xfract = (IFX << ell);
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assign Dfract = (IFD << mE);
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// Normalization shift: shift leading one into most significant bit
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assign Xnorm = (IFX << ell);
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assign Dnorm = (IFD << mE);
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//////////////////////////////////////////////////////
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// Integer Right Shift to digit boundary
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@ -133,10 +133,11 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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logic [P.LOGRK-1:0] IntTrunc, RightShiftX;
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logic [P.DIVBLEN:0] TotalIntBits, IntSteps;
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/* verilator lint_off WIDTH */
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// n = k*ceil((r+p)/rk) - 1
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assign TotalIntBits = P.LOGR + p; // Total number of result bits (r integer bits plus p fractional bits)
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assign IntTrunc = TotalIntBits % P.RK; // Truncation check for ceiling operator
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assign IntSteps = (TotalIntBits >> P.LOGRK) + |IntTrunc; // Number of steps for int div
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assign nE = (IntSteps * P.DIVCOPIES) - 1; // Fractional digits
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assign nE = (IntSteps * P.DIVCOPIES) - 1; // Fractional digits = total digits - 1 integer digit
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assign RightShiftX = P.RK - 1 - ((TotalIntBits - 1) % P.RK); // Right shift amount
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assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps
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/* verilator lint_on WIDTH */
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@ -150,18 +151,25 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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//////////////////////////////////////////////////////
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// Floating-Point Preprocessing
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// append leading 1 (for nonzero inputs)
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// Extend to Q4.b format
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// shift square root to be in range [1/4, 1)
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// Normalized numbers are shifted right by 1 if the exponent is odd
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// Subnormal numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
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// NOTE: there might be a discrepancy that X is never right shifted by 2. However
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// it comes out in the wash and gives the right answer. Investigate later if possible.
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// it comes out in the wash and gives the right answer. Investigate later if possible. ***
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//////////////////////////////////////////////////////
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assign DivX = {3'b000, Xfract};
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assign DivX = {3'b000, Xnorm}; // Zero-extend numerator for division
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// Sqrt is initialized on step one as R(X-1), so depends on Radix
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mux2 #(P.DIVb+1) sqrtxmux(Xfract, {1'b0, Xfract[P.DIVb:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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// If X = 0, then special case logic sets sqrt = 0 so this portion doesn't matter
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// Otherwise, X has a leading 1 after possible normalization shift and is now in range [1, 2)
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// Next X is shifted right by 1 or 2 bits to range [1/4, 1) and exponent will be adjusted accordingly to be even
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// Now (X-1) is negative. Formed by placing all 1s in all four integer bits (in Q4.b) form, keeping X in fraciton bits
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// Then multiply by R is left shift by r (1 or 2 for radix 2 or 4)
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// For Radix 2, this gives 3 leading 1s, followed by the fraction bits
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// For Radix 4, this gives 2 leading 1s, followed by the fraction bits (and a zero in the lsb)
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mux2 #(P.DIVb+1) sqrtxmux(Xnorm, {1'b0, Xnorm[P.DIVb:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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if (P.RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
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mux2 #(P.DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
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@ -177,11 +185,11 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) (
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end
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// Divisior register
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flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dfract}, D);
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flopen #(P.DIVb+4) dreg(clk, IFDivStartE, {3'b000, Dnorm}, D);
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// Floating-point exponent
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fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
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flopen #(P.NE+2) expreg(clk, IFDivStartE, QeE, QeM);
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fdivsqrtexpcalc #(P) expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Ue(UeE));
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flopen #(P.NE+2) expreg(clk, IFDivStartE, UeE, UeM);
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// Number of FSM cycles (to FSM)
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fdivsqrtcycles #(P) cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .CyclesE);
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@ -133,8 +133,8 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU)
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// divide signals
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logic [P.DIVb:0] QmM; // fdivsqrt signifcand
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logic [P.NE+1:0] QeM; // fdivsqrt exponent
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logic [P.DIVb:0] UmM; // fdivsqrt signifcand
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logic [P.NE+1:0] UeM; // fdivsqrt exponent
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logic DivStickyM; // fdivsqrt sticky bit
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logic FDivDoneE, IFDivStartE; // fdivsqrt control signals
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logic [P.XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU)
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@ -242,8 +242,8 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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fdivsqrt #(P) fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]),
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.XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE,
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.ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .IntDivE, .W64E,
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.StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM,
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.QmM, .FIntDivResultM);
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.StallM, .FlushE, .DivStickyM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .UeM,
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.UmM, .FIntDivResultM);
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// compare: fmin/fmax, flt/fle/feq
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fcmp #(P) fcmp (.Fmt(FmtE), .OpCtrl(OpCtrlE), .Xs(XsE), .Ys(YsE), .Xe(XeE), .Ye(YeE),
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@ -326,9 +326,9 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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//////////////////////////////////////////////////////////////////////////////////////////
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postprocess #(P) postprocess(.Xs(XsM), .Ys(YsM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM),
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.FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM),
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.FmaASticky(FmaAStickyM), .XZero(XZeroM), .YZero(YZeroM), .XInf(XInfM), .YInf(YInfM), .DivUm(UmM), .FmaSs(SsM),
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.ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM),
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.FmaSm(SmM), .DivQe(QeM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
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.FmaSm(SmM), .DivUe(UeM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM),
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.CvtCe(CeM), .CvtResSubnormUf(CvtResSubnormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM),
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.ToInt(FWriteIntM), .DivSticky(DivStickyM), .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM),
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.PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM));
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@ -27,8 +27,8 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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module divshiftcalc import cvw::*; #(parameter cvw_t P) (
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input logic [P.DIVb:0] DivQm, // divsqrt significand
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input logic [P.NE+1:0] DivQe, // divsqrt exponent
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input logic [P.DIVb:0] DivUm, // divsqrt significand
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input logic [P.NE+1:0] DivUe, // divsqrt exponent
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output logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt, // divsqrt shift amount
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output logic [P.NORMSHIFTSZ-1:0] DivShiftIn, // divsqrt shift input
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output logic DivResSubnorm, // is the divsqrt result subnormal
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@ -41,23 +41,23 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
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// is the result subnormal
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// if the exponent is 1 then the result needs to be normalized then the result is Subnormalizes
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assign DivResSubnorm = DivQe[P.NE+1]|(~|DivQe[P.NE+1:0]);
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assign DivResSubnorm = DivUe[P.NE+1]|(~|DivUe[P.NE+1:0]);
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// if the result is subnormal
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// 00000000x.xxxxxx... Exp = DivQe
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// .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1
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// .00xxxxxxxxxxxxx... << DivQe+NF+1 Exp = +1
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// 00000000x.xxxxxx... Exp = DivUe
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// .00000000xxxxxxx... >> NF+1 Exp = DivUe+NF+1
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// .00xxxxxxxxxxxxx... << DivUe+NF+1 Exp = +1
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// .0000xxxxxxxxxxx... >> 1 Exp = 1
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// Left shift amount = DivQe+NF+1-1
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assign DivSubnormShift = (P.NE+2)'(P.NF)+DivQe;
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// Left shift amount = DivUe+NF+1-1
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assign DivSubnormShift = (P.NE+2)'(P.NF)+DivUe;
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assign DivSubnormShiftPos = ~DivSubnormShift[P.NE+1];
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// if the result is normalized
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// 00000000x.xxxxxx... Exp = DivQe
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// .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1
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// 00000000.xxxxxxx... << NF Exp = DivQe+1
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// 00000000x.xxxxxx... << NF Exp = DivQe (extra shift done afterwards)
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// 00000000xx.xxxxx... << 1? Exp = DivQe-1 (determined after)
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// 00000000x.xxxxxx... Exp = DivUe
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// .00000000xxxxxxx... >> NF+1 Exp = DivUe+NF+1
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// 00000000.xxxxxxx... << NF Exp = DivUe+1
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// 00000000x.xxxxxx... << NF Exp = DivUe (extra shift done afterwards)
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// 00000000xx.xxxxx... << 1? Exp = DivUe-1 (determined after)
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// inital Left shift amount = NF
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// shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
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assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF);
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@ -68,5 +68,5 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
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assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
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// pre-shift the divider result for normalization
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assign DivShiftIn = {{P.NF{1'b0}}, DivQm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
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assign DivShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
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endmodule
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@ -48,8 +48,8 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
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input logic [$clog2(3*P.NF+5)-1:0] FmaSCnt, // the normalization shift count
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//divide signals
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input logic DivSticky, // divider sticky bit
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input logic [P.NE+1:0] DivQe, // divsqrt exponent
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input logic [P.DIVb:0] DivQm, // divsqrt significand
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input logic [P.NE+1:0] DivUe, // divsqrt exponent
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input logic [P.DIVb:0] DivUm, // divsqrt significand
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// conversion signals
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input logic CvtCs, // the result's sign
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input logic [P.NE:0] CvtCe, // the calculated expoent
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@ -91,7 +91,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
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// division singals
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logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount
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logic [P.NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input
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logic [P.NE+1:0] Qe; // divsqrt corrected exponent after corretion shift
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logic [P.NE+1:0] Ue; // divsqrt corrected exponent after corretion shift
|
||||
logic DivByZero; // divide by zero flag
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logic DivResSubnorm; // is the divsqrt result subnormal
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logic DivSubnormShiftPos; // is the divsqrt subnorm shift amout positive (not underflowed)
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@ -146,7 +146,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
|
||||
fmashiftcalc #(P) fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe,
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.FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn);
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divshiftcalc #(P) divshiftcalc(.DivQe, .DivQm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
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divshiftcalc #(P) divshiftcalc(.DivUe, .DivUm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn);
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// select which unit's output to shift
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always_comb
|
||||
@ -174,7 +174,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
|
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// correct for LZA/divsqrt error
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shiftcorrection #(P) shiftcorrection(.FmaOp, .FmaPreResultSubnorm, .NormSumExp,
|
||||
.DivResSubnorm, .DivSubnormShiftPos, .DivOp, .DivQe, .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf);
|
||||
.DivResSubnorm, .DivSubnormShiftPos, .DivOp, .DivUe, .Ue, .FmaSZero, .Shifted, .FmaMe, .Mf);
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// Rounding
|
||||
@ -189,7 +189,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
|
||||
// calulate result sign used in rounding unit
|
||||
roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
|
||||
|
||||
round #(P) round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Qe,
|
||||
round #(P) round(.OutFmt, .Frm, .FmaASticky, .Plus1, .PostProcSel, .CvtCe, .Ue,
|
||||
.Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResSubnormUf, .Mf, .ToInt, .CvtResUf,
|
||||
.DivSticky, .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .Sticky, .Round, .Guard, .Me);
|
||||
|
||||
|
||||
@ -39,7 +39,7 @@ module round import cvw::*; #(parameter cvw_t P) (
|
||||
// divsqrt
|
||||
input logic DivOp, // is a division opperation being done
|
||||
input logic DivSticky, // divsqrt sticky bit
|
||||
input logic [P.NE+1:0] Qe, // the divsqrt calculated expoent
|
||||
input logic [P.NE+1:0] Ue, // the divsqrt calculated expoent
|
||||
// cvt
|
||||
input logic CvtOp, // is a convert opperation being done
|
||||
input logic ToInt, // is the cvt op a cvt to integer
|
||||
@ -300,8 +300,8 @@ module round import cvw::*; #(parameter cvw_t P) (
|
||||
case(PostProcSel)
|
||||
2'b10: Me = FmaMe; // fma
|
||||
2'b00: Me = {CvtCe[P.NE], CvtCe}&{P.NE+2{~CvtResSubnormUf|CvtResUf}}; // cvt
|
||||
// 2'b01: Me = DivDone ? Qe : '0; // divide
|
||||
2'b01: Me = Qe; // divide
|
||||
// 2'b01: Me = DivDone ? Ue : '0; // divide
|
||||
2'b01: Me = Ue; // divide
|
||||
default: Me = '0;
|
||||
endcase
|
||||
|
||||
|
||||
@ -31,7 +31,7 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
|
||||
// divsqrt
|
||||
input logic DivOp, // is it a divsqrt opperation
|
||||
input logic DivResSubnorm, // is the divsqrt result subnormal
|
||||
input logic [P.NE+1:0] DivQe, // the divsqrt result's exponent
|
||||
input logic [P.NE+1:0] DivUe, // the divsqrt result's exponent
|
||||
input logic DivSubnormShiftPos, // is the subnorm divider shift amount positive (ie not underflowed)
|
||||
//fma
|
||||
input logic FmaOp, // is it an fma opperation
|
||||
@ -41,7 +41,7 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
|
||||
// output
|
||||
output logic [P.NE+1:0] FmaMe, // exponent of the normalized sum
|
||||
output logic [P.CORRSHIFTSZ-1:0] Mf, // the shifted sum before LZA correction
|
||||
output logic [P.NE+1:0] Qe // corrected exponent for divider
|
||||
output logic [P.NE+1:0] Ue // corrected exponent for divider
|
||||
);
|
||||
|
||||
logic [3*P.NF+3:0] CorrSumShifted; // the shifted sum after LZA correction
|
||||
@ -61,7 +61,7 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
// correct the shifting of the divsqrt caused by producing a result in (2, .5] range
|
||||
// condition: if the msb is 1 or the exponent was one, but the shifted quotent was < 1 (Subnorm)
|
||||
assign LeftShiftQm = (LZAPlus1|(DivQe==1&~LZAPlus1));
|
||||
assign LeftShiftQm = (LZAPlus1|(DivUe==1&~LZAPlus1));
|
||||
assign CorrQm0 = Shifted[P.NORMSHIFTSZ-3:P.NORMSHIFTSZ-P.CORRSHIFTSZ-2];
|
||||
assign CorrQm1 = Shifted[P.NORMSHIFTSZ-2:P.NORMSHIFTSZ-P.CORRSHIFTSZ-1];
|
||||
mux2 #(P.CORRSHIFTSZ) divcorrmux(CorrQm0, CorrQm1, LeftShiftQm, CorrQmShifted);
|
||||
@ -87,5 +87,5 @@ module shiftcorrection import cvw::*; #(parameter cvw_t P) (
|
||||
|
||||
// the quotent is in the range [.5,2) if there is no early termination
|
||||
// if the quotent < 1 and not Subnormal then subtract 1 to account for the normalization shift
|
||||
assign Qe = (DivResSubnorm & DivSubnormShiftPos) ? '0 : DivQe - {(P.NE+1)'(0), ~LZAPlus1};
|
||||
assign Ue = (DivResSubnorm & DivSubnormShiftPos) ? '0 : DivUe - {(P.NE+1)'(0), ~LZAPlus1};
|
||||
endmodule
|
||||
|
||||
Loading…
Reference in New Issue
Block a user