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939 Commits

Author SHA1 Message Date
Thomas Fleming
38236e9172 Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
6d1a6694a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 13:20:12 -04:00
bbracker
74b35ac57a greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Ross Thompson
d8ab7a5de2 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
00b3e36b30 Refactor tlb_ram to use flop primitives 2021-04-22 01:52:43 -04:00
Thomas Fleming
ef80176e2c Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Domenico Ottolia
fb8f244dab Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
e336fbd108 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
4bae666fa1 Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Ross Thompson
7b3735fc25 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Teo Ene
ddc98e7d08 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Ross Thompson
532c8771ba major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Domenico Ottolia
bf86a809eb Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
f3093ac612 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
99424fb983 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
251ece20fe Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Domenico Ottolia
0c307d2db1 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Jarred Allen
850f728cc7 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Katherine Parry
d12eb0f4eb fixed synth bugs in fpu 2021-04-19 00:39:16 +00:00
Noah Boorstin
9bb1233433 neat verilog thing 2021-04-18 17:48:51 -04:00
Jarred Allen
aef57cab50 dcache lints 2021-04-15 21:13:56 -04:00
bbracker
290b3424e5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
9f13ee3f31 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
92bb38fa8c Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Teo Ene
2814579f30 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
374a93dae6 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e780694ee0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
6dd7591ceb Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Thomas Fleming
ff9f1e5e72 Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
ad86295fcf Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
636e2de9df integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Jarred Allen
81c02bda55 Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Ross Thompson
87b716170c Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
0369fc5d1e Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
6d4042e479 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
7e9a0602ea fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
e69cc0d23a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
51cdff3e9b csri lint improvement 2021-04-15 09:05:53 -04:00
Jarred Allen
3717699ad9 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Thomas Fleming
3c49fd08f6 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
892dfd5a9b More icache bugfixes 2021-04-14 19:03:33 -04:00
Jarred Allen
c1e2e58ebe Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Thomas Fleming
7d2d6823f1 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
0a9b208729 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
ef011496a7 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
09c9c49541 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
dc8a165806 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
1018a10625 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
4ae1df1290 Merge branch 'main' into cache 2021-04-13 01:10:03 -04:00
Jarred Allen
fc8b8ad7aa A few more cache fixes 2021-04-13 01:07:40 -04:00
Ross Thompson
35f8b4f74f Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Katherine Parry
f4cb92ae71 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
27cb94e7af fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
Domenico Ottolia
65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
fc39535e4e Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
c54aecde73 Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
4322694f7a Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
Ross Thompson
c91436d3b7 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c Merge remote-tracking branch 'refs/remotes/origin/tests' into tests 2021-04-06 21:20:55 -05:00
Jarred Allen
bd8f1eea3c Fix another bug in icache 2021-04-06 17:47:00 -04:00
Jarred Allen
3afc358974 Fix another bug in icache 2021-04-06 12:48:42 -04:00
bbracker
38017e6aae declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
a4c3afb847 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
4a5aa5b202 plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
e6a7353847 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
6b43381c38 Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
8dfec29f7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Thomas Fleming
1cbdaf1f05 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Jarred Allen
c95da7d11e Fix bug in icache 2021-04-03 18:10:54 -04:00
Katherine Parry
d7b1379ab8 Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
d21006d048 Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
362f6ea2e6 Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
bfb4b051c6 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Jarred Allen
5afb255251 Begin changes to direct-mapped cache 2021-04-01 13:55:21 -04:00
Shreya Sanghai
df149d1be7 fixed minor bugs in localHistory 2021-04-01 13:40:08 -04:00
James E. Stine
0495195d68 Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
ShreyaSanghai
28a9c6ba56 added localHistoryPredictor 2021-04-01 22:22:40 +05:30
Shreya Sanghai
b544526766 fixed bugs in global history to read latest GHRE 2021-03-31 21:56:14 -04:00
Ross Thompson
9172e52286 Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
77b8e27205 Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
2a308309e4 fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
Noah Boorstin
b5a1691c2b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Jarred Allen
39bf2347bc Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
32829bf7a1 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
5f4feb0ff1 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Jarred Allen
3b4f0141f4 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Brett Mathis
162f2df880 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Jarred Allen
0290568a52 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
Jarred Allen
ce6f102fc5 Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
128278ea27 Working for all of rv64i now, but not compressed instructions 2021-03-25 13:02:26 -04:00
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
ba95557c44 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
ad0d77e9e1 Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
ebd6b931c6 Fix bug in cache line 2021-03-25 12:59:30 -04:00
Jarred Allen
b774d35c34 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
4b92a595ab Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
b5fa410e15 added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
682050a33b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
67b27cd2f5 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
e98dd420bc future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822 Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Katherine Parry
18cb1f4873 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Ross Thompson
a99c0502e5 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Jarred Allen
c1fe16b70b Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Jarred Allen
a51257abca Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Ross Thompson
1c6e37120e Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Jarred Allen
4410944049 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
84ad1353e4 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Katherine Parry
56dc8de009 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Ross Thompson
4fb7a1e0a6 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. 2021-03-23 20:20:23 -05:00
Ross Thompson
49348d734b fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
95dbc5f1fa fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Jarred Allen
d6ecc3ede0 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00
Teo Ene
ef3d2dda48 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
0f8fe8fb3b Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
6ffa01cc4d Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
827993598d Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
15474f678d Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
bbracker
5efd5958e7 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
6ce52f9b80 Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Jarred Allen
3748d03adc Merge branch 'main' into cache 2021-03-22 13:47:48 -04:00
bbracker
11d4a8ab34 first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
f741ba7702 fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Jarred Allen
f9cf05a7d4 Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
a3a646d1a9 Merge branch 'main' into cache 2021-03-20 17:56:25 -04:00
Jarred Allen
a2bf5ac202 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
c5f99c4a34 Revert "Change flop to listen to StallF" 
This reverts commit c8028710a5.
 2021-03-20 17:34:19 -04:00
Jarred Allen
c8028710a5 Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Katherine Parry
e317e7511e messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
bbracker
85363e941d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
bbracker
98e93a63c0 maybe AHB works now 2021-03-18 17:47:00 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
8d484174a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Noah Boorstin
bc1a0c6ee7 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e everyone gets a bootram 2021-03-18 12:35:37 -04:00
Shreya Sanghai
36f0631203 added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Jarred Allen
a82aa23399 Fix icache for jumping into misaligned instructions 2021-03-16 16:57:51 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
2d2092e8ab Merge remote-tracking branch 'origin/main' into cache 2021-03-16 14:17:39 -04:00
Shreya Sanghai
08e9149e20 made performance counters count branch misprediction 2021-03-16 11:24:17 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Jarred Allen
ac9fd5a323 Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
deb13f34bb Get non-jump case working 2021-03-14 14:46:21 -04:00
bbracker
e58d17d5b7 slightly smarter dtim HREADY 2021-03-13 07:03:33 -05:00
bbracker
345254b5a3 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
c5015e5809 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
bbracker
f4fb546969 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3 Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Thomas Fleming
1294235837 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
42275e92ed Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Noah Boorstin
2c25e270a2 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
Jarred Allen
ae9bcc174d Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
3172be3039 More progress 2021-03-09 21:16:07 -05:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
David Harris
9c7da510fb Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Ross Thompson
87ed6d510c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Thomas Fleming
be6ee84d87 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 15:46:51 -05:00
Noah Boorstin
86142e764a Merge branch 'main' into busybear 2021-03-05 20:27:19 +00:00
bbracker
850a2e9329 added a delay to sel signals 2021-03-05 15:07:34 -05:00
bbracker
77e2e357a7 more merging fixes 2021-03-05 14:36:07 -05:00
bbracker
ed4ff1ecd0 remove deprecated mem signals 2021-03-05 14:27:38 -05:00
bbracker
0f4a231543 first merge of ahb fix 2021-03-05 14:24:22 -05:00
Thomas Fleming
2e2eb5839f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
8c97143be6 Place tlb parameters into constant header file 2021-03-05 13:35:24 -05:00
Thomas Fleming
7e11317a2d Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Noah Boorstin
f48af209c4 busybear: make CSRs only weird for us 2021-03-05 00:46:32 +00:00
Ross Thompson
a662aa487c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-04 17:31:27 -06:00
Jarred Allen
41f682f848 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Noah Boorstin
dfae278ffb busybear: make imperas tests work again 2021-03-04 22:44:49 +00:00
Katherine Parry
cfac6bf0c7 fixed various bugs 2021-03-04 22:20:39 +00:00
Katherine Parry
09564f1c77 fixed various bugs 2021-03-04 22:20:28 +00:00
Katherine Parry
a6bc39b5ad fixed various bugs 2021-03-04 22:20:23 +00:00
Katherine Parry
526e3f5996 fixed various bugs 2021-03-04 22:20:02 +00:00
Katherine Parry
1e906b36a0 fixed various bugs 2021-03-04 22:19:21 +00:00
Katherine Parry
3fb0f323b8 fixed various bugs 2021-03-04 22:18:47 +00:00
Katherine Parry
fdfc0dbf46 fixed various bugs 2021-03-04 22:18:19 +00:00
Jarred Allen
106718b196 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Thomas Fleming
3303a013ef Merge branch 'walker' into main 2021-03-04 15:27:03 -05:00
Noah Boorstin
735c6789ea busybear: comment out instraccessfaultf for imem for now 2021-03-04 20:26:41 +00:00
Noah Boorstin
827dfd774b Merge branch 'main' into busybear 
Conflicts:
	wally-pipelined/src/uncore/imem.sv
 2021-03-04 20:16:03 +00:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
4d14c714a7 Fixed forwarding around the 2 bit predictor. 2021-03-04 13:01:41 -06:00
Shreya Sanghai
246dbd05e7 fixed bugs 2021-03-04 12:59:45 -05:00
Shreya Sanghai
f0ec365117 added performance counters 2021-03-04 11:42:52 -05:00
Ross Thompson
52d95d415f Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
de3f2547f4 Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1df7151fb6 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Thomas Fleming
2e409f2299 Merge branch 'tlb_toy' into main 2021-03-04 02:41:11 -05:00
Thomas Fleming
5f98c932bf Move tlb into mmu directory 2021-03-04 02:39:08 -05:00
Teo Ene
f060f6cb9d Fix to 32-bit option of commit babe6ce9db 2021-03-04 01:33:34 -06:00
Thomas Fleming
d9f396ee0e Merge branch 'main' into tlb_toy 2021-03-04 01:18:04 -05:00
Thomas Fleming
347275e7ee Generalize tlb module 
- number of tlb entries is now parameterized
- tlb now supports rv64i
 2021-03-04 01:13:31 -05:00
Thomas Fleming
394051c02f Begin hardware page table walker 2021-03-03 17:13:45 -05:00
Noah Boorstin
62b441f3f5 busybear: probably discovered bug in ahb code 2021-03-01 20:56:04 +00:00
Noah Boorstin
4833b36535 busybear: more adapting to new memory system 2021-03-01 18:50:42 +00:00
Noah Boorstin
26d4024b33 busybear: fix bootram range 2021-03-01 17:45:21 +00:00
David Harris
9bcddfa5dd Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-01 00:09:55 -05:00
David Harris
2543c29839 Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
Teo Ene
babe6ce9db Properly implemented the fix from commit 31c07b2adc 2021-02-28 22:22:04 -06:00
Noah Boorstin
bcc0010498 Merge branch 'main' into busybear 2021-02-28 20:45:08 +00:00
Noah Boorstin
f306d2d2e1 busybear: start preloading bootmem 2021-02-28 20:43:57 +00:00
Noah Boorstin
a03796a519 busybear: change sstatus, mstatus reset value 2021-02-28 16:19:03 +00:00
Noah Boorstin
6e70ae8b3d busybear: add 2nd dtim for bootram 2021-02-28 16:08:54 +00:00
Noah Boorstin
edd5e9106d busybear: remove gpio, start adding 2nd ram 2021-02-28 06:02:40 +00:00
Noah Boorstin
e5e345d161 busybear: instantiate normal wallypipelinedsoc 2021-02-28 06:02:21 +00:00
Ross Thompson
7592a0dacb Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
David Harris
015b632eb1 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
kaveh pezeshki
c7863d58cd merged with main to integrate with AHB 2021-02-26 05:37:10 -08:00
David Harris
b16846bddb Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
24f767a404 Retimed peripherals for AHB interface 2021-02-26 00:55:41 -05:00
David Harris
c060e427f0 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-25 15:49:38 -05:00
David Harris
a16fd95eed Restored to working multiplier after Lab 2 2021-02-25 15:32:43 -05:00
Brett Mathis
ec82453ba1 FPU Assembly tests 2021-02-25 14:32:36 -06:00
Teo Ene
6be5bb1f84 Fixed previous commit 2021-02-25 11:24:44 -06:00
Teo Ene
31c07b2adc Edited imem to account for TIMBASE==0; still hard-coded and needs to be improved, but works with coremark config now. 2021-02-25 11:23:01 -06:00
David Harris
d00d42cf9a Merged bus into main 2021-02-25 00:28:41 -05:00
David Harris
f5e9c91193 All tests passing with bus interface 2021-02-24 07:25:03 -05:00
Katherine Parry
8f5cc19143 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-23 20:21:53 +00:00
Katherine Parry
7b103423e1 inital FMA push 2021-02-23 20:19:12 +00:00
Noah Boorstin
ceb7df3561 busybear: instantiate soc instead of hart 2021-02-23 18:59:06 +00:00
David Harris
c52a99ce2d Fixed fetch stall after jump in bus unit 2021-02-23 09:08:57 -05:00
David Harris
817f81c356 Debugging Bus interface 2021-02-22 13:48:30 -05:00
kaveh pezeshki
62d9185212 Merge remote-tracking branch 'origin/tlb_toy' into busybear 2021-02-22 02:23:01 -08:00
Ross Thompson
9b3637bd87 RAS needs to be reset or preloaded. For now I just reset it. 
Fixed bug with the instruction class.
Most tests now pass.  Only Wally-JAL and the compressed instruction tests fail.  Currently the bpred does not support compressed.  This will be in the next version.
 2021-02-19 20:09:07 -06:00
Ross Thompson
00de91cc87 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
c6ebe7733b Hacked the sram memory models to reset their internal registers. This allows the simulation to run but is only temporary. 
About 149307ns of simulation run.
 2021-02-18 21:32:15 -06:00
Thomas Fleming
21552eaf9d Create simple TLB 
This TLB is just a demonstration and is not currently
instantiated by the IFU or DFU.
 2021-02-18 18:06:09 -05:00
David Harris
acd7ba8b60 Updated creation date of mul 2021-02-18 08:13:08 -05:00
Ross Thompson
5df7e959f3 Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
2f5b4c3a25 Resotred part of multiplier for lab 2 2021-02-17 16:14:04 -05:00
David Harris
64536dbc34 Removed multiplier for lab 2 2021-02-17 16:06:16 -05:00
David Harris
dc758a0c7b Multiplier tweaks 2021-02-17 16:00:27 -05:00
David Harris
3edf910c18 Started to integrate OSU divider 2021-02-17 15:38:44 -05:00
David Harris
cb0054b524 Multiply instructions working 2021-02-17 15:29:20 -05:00
Noah Boorstin
5835641c6c busybear testbench: check (almost) all the CSRs 2021-02-16 20:03:24 -05:00
David Harris
8dec69c2ce Added MUL 2021-02-15 22:27:35 -05:00
Ross Thompson
78db3654c6 We now have a solid rough draft of the 2 bit sat counter branch predictor with BTB and RAS. 
This is not yet tested but the system verilog does compile.
 2021-02-15 14:51:39 -06:00
David Harris
37dba8fd26 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
Ross Thompson
3ec1f668fc added branch predictor 2 bit table + SRAM model. The SRAM model is only approximate, but it does correctly model the read and write pipelined behavior. 2021-02-14 15:13:55 -06:00
Ross Thompson
30df1cdd25 The top level of the branch predictor built and compiles. Does not yet function. Missing the BTB, RAS, and direction prediction tables. 2021-02-14 11:06:31 -06:00
bbracker
9231646fb3 bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
David Harris
183a2dcfb5 Debugging bus interface. 2021-02-10 01:43:54 -05:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
63c7c18771 Fixed lw by delaying read value by one cycle 2021-02-07 23:28:21 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
Noah Boorstin
14cde0d59c Change CSR reset and available bits to conform to OVPsim 
Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.
 2021-02-04 22:03:45 +00:00
Brett Mathis
79cb7ed571 Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
David Harris
91f6858de7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 19:44:43 -05:00
David Harris
a44c2abb12 Minor tweaks 2021-02-02 19:44:37 -05:00
Noah Boorstin
00d9e13d68 same thing but do that right this time 2021-02-02 21:47:15 +00:00
Noah Boorstin
56ff32f857 change undefined syntax in extend.sv 
don't need verilator execption anymore
 2021-02-02 21:39:20 +00:00
David Harris
d56d7a75a6 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
aee44bb343 Changed DTIM latency to 2 cycles 2021-02-02 14:22:12 -05:00
David Harris
4fbb5f0f1b Cleaned up hazard interface 2021-02-02 13:53:13 -05:00
David Harris
c23afbda3a Moved LoadStall generation to IEU 2021-02-02 13:42:23 -05:00
David Harris
aad1d3d7dd Moved writeback pipeline registers from datapth into DMEM and CSR 2021-02-02 13:02:31 -05:00
David Harris
9d7e242596 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
Brett Mathis
94de3e9fb2 OSU FPU IP initial commit 2021-02-01 19:33:43 -06:00
David Harris
056b147b13 Renamed DCU to DMEM 2021-02-01 18:52:22 -05:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
fc1fb94217 Working on reading instruction from TIM 2021-01-30 01:57:51 -05:00
David Harris
61fd7c4499 Adding stalls for memory delays 2021-01-30 01:43:49 -05:00
David Harris
9c81278f28 Added HCLK and HRESETn 2021-01-30 00:56:12 -05:00
David Harris
a357f2a0e7 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
73a584b223 Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team 2021-01-29 18:06:36 -05:00
David Harris
e700e404c9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-29 17:29:01 -05:00
David Harris
9a51bb27c3 Implemented adrdec for uncore 2021-01-29 17:28:53 -05:00
Teo Ene
9eafdbe349 - Removed latch on CSRCReadValM in csrc.sv 
- Changed top level to wallypipelinedhart
 2021-01-29 15:56:51 -06:00
David Harris
dc2443c55b Moving data memory to uncore 2021-01-29 15:37:51 -05:00
David Harris
ed3cb83c10 Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
David Harris
618c6e4813 Renamed modules in privileged unit 2021-01-28 23:21:12 -05:00
David Harris
05b755958f Hint to optimize ifu 2021-01-28 21:40:48 -05:00
David Harris
fe0876027f Fixed floating signals in clint and ieu 2021-01-28 15:44:05 -05:00
David Harris
ad5d4793b6 Fixed c.jr instruction improperly writing ra 2021-01-28 15:18:23 -05:00
David Harris
f95d0690ca Created DCU and moved memdp into DCU 2021-01-28 01:03:12 -05:00
David Harris
a50b6c2a15 Provided PC + 2 or 4 (PCLink) for JAL 2021-01-28 00:22:05 -05:00
David Harris
824014c5c0 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
David Harris
616afaba69 Moved privileged unit from datapath to hart 2021-01-27 07:46:52 -05:00
David Harris
b88508ca11 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
David Harris
1d9c741c00 Reset Vector moved to config file 2021-01-25 15:57:36 -05:00
David Harris
fa18052348 Added test configurations 2021-01-25 11:28:43 -05:00
Noah Boorstin
aea1c0cd2e small busybear testbench changes 2021-01-24 20:43:47 -05:00
Noah Boorstin
e7288716f7 Linux testbench works now 
Added parameterized PCSTART to allow compatibility between imperas and busybear tests
Hopefully we are done with the "busybear" branch, please don't use it for future work
 2021-01-24 17:10:00 -05:00
Noah Boorstin
12a8f83025 Merge branch 'busybear' into main 
Merging busybear testbench into main, keeping main edits of wally src
 2021-01-24 16:28:36 -05:00
Noah Boorstin
b08b86f561 sucessfully simulate first 30 instructions 
still need to find a better solution to InstrAccessFault/DataAccessFault though
 2021-01-23 19:01:44 -05:00
Noah Boorstin
a75d7e4555 More linux testbench fixes 
So I'm super sorry for accidently overwriting the commits this morning
Need to be more careful with force pushing :(

This fixes the problem with CSRR somehow, by tying InstrAccessFaultF and
DataAccessFaultM to zero for now. I feel like this is not a good solution
and will cause problems in the future, but for the start it seems to work for now.
I'm fair certain we need these to accurately simulate to do linux properly.

Anyway, this super hackish solution is in place for now, now on to ignoring mispredicted reads
 2021-01-23 17:52:05 -05:00
Noah Boorstin
be62987dec Linux test now gets through first 8 instructions! 
fixes the python parser:
  get the value, not function name, of PC
  only write changes to registers instead of registers every cycle
temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this
dont stop on errors, print them prettier
 2021-01-23 16:46:45 -05:00
David Harris
3905e77e54 Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh 2021-01-23 10:48:12 -05:00
David Harris
170c88bc06 Cleaned up regfile x0 tied to gnd 2021-01-23 10:22:20 -05:00
David Harris
93f8c6f29e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-01-23 10:19:28 -05:00
David Harris
6b9c6223be Initial checkin of UART 2021-01-23 10:19:09 -05:00
Noah Boorstin
18f6aa716e slightly more info on errors, add instruction decoding 2021-01-22 21:14:45 -05:00
Noah Boorstin
3b16766fde change how testbench reads data 
we're not sure if this is a good idea, but for now, we broke things up into 3 seperate
files, each read seperately. One for pc and instructions, one for registers, and one for
memory reads. Each is scrolled through essentially independantly: new pc data is read and checked
whenever pc changes, new register data is checked whenever any register changes, and a new mem
read value is gotten whenever DataAdrM or MemRWM changes and MemRWM is not zero. I'm not super
sure about the last one. Currently it looks like things should be working, but it goes wrong after,
like, 3 instructions.
 2021-01-22 20:27:01 -05:00
Noah Boorstin
4c51a20634 change regfile to not hold state of x0 2021-01-22 15:12:33 -05:00
Noah Boorstin
2c8571aaac change regfile to not hold state of x0 2021-01-22 15:11:55 -05:00
Noah Boorstin
e45f452f25 Start adding register checking 
I'm now realizing we need to simulate loads, or else these will all be wrong
 2021-01-22 15:11:13 -05:00
Noah Boorstin
8104b93900 load instructions from file line by line 2021-01-22 14:11:17 -05:00
Noah Boorstin
40f0b1e328 More testbench setup work 
- Copy bare-bones testbench from E85
   - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
 - Create .gitignore for vsim files
 - Make PC reset a macro, change to 0x1000 to conform to the bootloader

I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo

for now it lives in /mnt/scratch/riscv_testbench/
 2021-01-21 17:55:05 -05:00
Noah Boorstin
795359576b copy testbench to modify for busybear 2021-01-21 16:17:34 -05:00
David Harris
f32c70e866 testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64 2021-01-20 01:04:28 -05:00
David Harris
6595c7827f Changed to . notation for instantiation, cleaned up dmem 2021-01-18 20:16:53 -05:00
David Harris
bfc86182a0 Added GPIO 2021-01-15 00:25:56 -05:00
David Harris
821fb20746 Added GPIO 2021-01-15 00:19:31 -05:00
David Harris
fd01e27a48 Initial Checkin 2021-01-14 23:37:51 -05:00