cvw/wally-pipelined/src
Ross Thompson 00de91cc87 Added FlushF to hazard unit.
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
2021-02-19 16:36:51 -06:00
..
dmem Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
ebu Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
fpu/build_temp Parallel FSR's and F CTRL logic 2021-02-04 02:25:55 -06:00
generic Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
hazard Added FlushF to hazard unit. 2021-02-19 16:36:51 -06:00
ieu Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-02-02 19:44:43 -05:00
ifu Added FlushF to hazard unit. 2021-02-19 16:36:51 -06:00
privileged Minor tweaks 2021-02-02 19:44:37 -05:00
uncore bus rw bugfix and peripherals testing 2021-02-12 00:02:45 -05:00
wally Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00