cvw/wally-pipelined/src
2021-01-29 23:43:48 -05:00
..
adrdec.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
ahblite.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
alu.sv
clint.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
controller.sv Moving data memory to uncore 2021-01-29 15:37:51 -05:00
csr.sv
csrc.sv - Removed latch on CSRCReadValM in csrc.sv 2021-01-29 15:56:51 -06:00
csri.sv
csrm.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
csrn.sv
csrs.sv Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team 2021-01-29 18:06:36 -05:00
csrsr.sv
csru.sv
datapath.sv Moving data memory to uncore 2021-01-29 15:37:51 -05:00
dcu.sv Moving data memory to uncore 2021-01-29 15:37:51 -05:00
decompress.sv Fixed c.jr instruction improperly writing ra 2021-01-28 15:18:23 -05:00
dtim.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
extend.sv
flop.sv
gpio.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
hazard.sv
ieu.sv Moving data memory to uncore 2021-01-29 15:37:51 -05:00
ifu.sv Hint to optimize ifu 2021-01-28 21:40:48 -05:00
imem.sv
mux.sv
privdec.sv Renamed modules in privileged unit 2021-01-28 23:21:12 -05:00
privileged.sv Renamed modules in privileged unit 2021-01-28 23:21:12 -05:00
regfile.sv
shifter.sv
subwordread.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
subwordwrite.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
trap.sv Created DCU and moved memdp into DCU 2021-01-28 01:03:12 -05:00
uart.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
uartPC16550D.sv Added ahblite bus interface unit 2021-01-29 01:07:17 -05:00
uncore.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
wallypipelinedhart.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
wallypipelinedsoc.sv Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00