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alu.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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clint.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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controller.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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csr.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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csrc.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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csri.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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csrm.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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csrn.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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csrs.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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csrsr.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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csru.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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datapath.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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dmem.sv
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testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64
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2021-01-20 01:04:28 -05:00 |
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dtim.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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extend.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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flop.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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gpio.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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hazard.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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imem.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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instrDecompress.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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memdp.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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mux.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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pclogic.sv
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More testbench setup work
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2021-01-21 17:55:05 -05:00 |
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privileged.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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privilegeDecoder.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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privilegeModeReg.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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regfile.sv
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change regfile to not hold state of x0
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2021-01-22 15:11:55 -05:00 |
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shifter.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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testbench-busybear.sv
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slightly more info on errors, add instruction decoding
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2021-01-22 21:14:45 -05:00 |
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testbench.sv
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testgen-ADD-SUB working and testbench simualtes with new vectors for rv32 and rv64
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2021-01-20 01:04:28 -05:00 |
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trap.sv
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Initial Checkin
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2021-01-14 23:37:51 -05:00 |
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wally-macros.sv
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More testbench setup work
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2021-01-21 17:55:05 -05:00 |
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wallypipelined.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
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wallypipelinedhart.sv
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Changed to . notation for instantiation, cleaned up dmem
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2021-01-18 20:16:53 -05:00 |
