Shreya Sanghai 08e9149e20 made performance counters count branch misprediction		2021-03-16 11:24:17 -04:00
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dmem	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-11 00:15:58 -05:00
ebu	64-bit AMO debugged	2021-03-11 23:18:33 -05:00
fpu	fixed various bugs	2021-03-04 22:20:39 +00:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Merge branch 'bp' into main	2021-03-04 13:35:46 -06:00
ieu	64-bit AMO debugged	2021-03-11 23:18:33 -05:00
ifu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-12 14:58:04 -06:00
mmu	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00
muldiv	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
privileged	made performance counters count branch misprediction	2021-03-16 11:24:17 -04:00
tlb_toy	Install tlb into ifu	2021-03-04 03:11:34 -05:00
uncore	slightly smarter dtim HREADY	2021-03-13 06:55:34 -05:00
wally	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-11 00:15:58 -05:00