Noah Boorstin 14cde0d59c Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.		2021-02-04 22:03:45 +00:00
..
dmem	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
ebu	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
generic	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00
hazard	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
ieu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-02-02 19:44:43 -05:00
ifu	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
privileged	Change CSR reset and available bits to conform to OVPsim	2021-02-04 22:03:45 +00:00
uncore	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
wally	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00