forked from Github_Repos/cvw
Linux test now gets through first 8 instructions!
fixes the python parser: get the value, not function name, of PC only write changes to registers instead of registers every cycle temporarilly NOP out CSRR instruction (with the canonical NOP), that was breaking this dont stop on errors, print them prettier
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@ -81,8 +81,8 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
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scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]);
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// check things!
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if (rf[j*64+63 -: 64] != rfExpected[j]) begin
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$display("%t ps: rf[%i] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]);
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$stop;
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$display("%t ps: rf[%0d] does not equal rf expected: %x, %x", $time, j, rf[j*64+63 -: 64], rfExpected[j]);
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// $stop;
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end
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end
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end
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@ -103,7 +103,7 @@ module testbench_busybear #(parameter XLEN=64, MISA=32'h00000104, ZCSR = 1, ZCOU
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//check things!
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if (PCF != pcExpected) begin
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$display("%t ps: PC does not equal PC expected: %x, %x", $time, PCF, pcExpected);
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$stop;
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// $stop;
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end
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end
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@ -77,14 +77,14 @@ add wave -hex /testbench_busybear/dut/dp/regf/rf[28]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[29]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[30]
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add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
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#add wave /testbench_busybear/InstrFName
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add wave /testbench_busybear/InstrFName
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##add wave -hex /testbench_busybear/dut/dp/PCD
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#add wave -hex /testbench_busybear/dut/dp/InstrD
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#add wave /testbench_busybear/InstrDName
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add wave /testbench_busybear/InstrDName
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#add wave -divider
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##add wave -hex /testbench_busybear/dut/dp/PCE
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##add wave -hex /testbench_busybear/dut/dp/InstrE
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#add wave /testbench_busybear/InstrEName
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add wave /testbench_busybear/InstrEName
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#add wave -hex /testbench_busybear/dut/dp/SrcAE
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#add wave -hex /testbench_busybear/dut/dp/SrcBE
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#add wave -hex /testbench_busybear/dut/dp/ALUResultE
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@ -92,14 +92,14 @@ add wave -hex /testbench_busybear/dut/dp/regf/rf[31]
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#add wave -divider
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##add wave -hex /testbench_busybear/dut/dp/PCM
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##add wave -hex /testbench_busybear/dut/dp/InstrM
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#add wave /testbench_busybear/InstrMName
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add wave /testbench_busybear/InstrMName
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#add wave /testbench_busybear/dut/dmem/dtim/memwrite
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#add wave -hex /testbench_busybear/dut/dmem/AdrM
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#add wave -hex /testbench_busybear/dut/dmem/WriteDataM
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#add wave -divider
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#add wave -hex /testbench_busybear/dut/dp/PCW
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##add wave -hex /testbench_busybear/dut/dp/InstrW
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#add wave /testbench_busybear/InstrWName
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add wave /testbench_busybear/InstrWName
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#add wave /testbench_busybear/dut/dp/RegWriteW
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#add wave -hex /testbench_busybear/dut/dp/ResultW
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#add wave -hex /testbench_busybear/dut/dp/RdW
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