cvw/wally-pipelined/src
2021-03-23 20:06:45 -05:00
..
dmem Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
ebu first pass at PLIC interface 2021-03-22 10:14:21 -04:00
fpu fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
generic change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
hazard Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00
ieu removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
ifu fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
mmu Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
muldiv Cleaned out unused signals 2021-02-26 09:17:36 -05:00
privileged PC counts branch instructions 2021-03-23 14:25:51 -04:00
tlb_toy Install tlb into ifu 2021-03-04 03:11:34 -05:00
uncore added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
wally PC counts branch instructions 2021-03-23 14:25:51 -04:00