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adrdec.sv
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Connected AHB bus to Uncore
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2021-01-29 23:43:48 -05:00 |
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ahblite.sv
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Working on reading instruction from TIM
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2021-01-30 01:57:51 -05:00 |
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alu.sv
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Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
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2021-01-23 10:48:12 -05:00 |
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clint.sv
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
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controller.sv
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Moving data memory to uncore
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2021-01-29 15:37:51 -05:00 |
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csr.sv
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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csrc.sv
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
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csri.sv
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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csrm.sv
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Connected AHB bus to Uncore
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2021-01-29 23:43:48 -05:00 |
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csrn.sv
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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csrs.sv
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Added SATP, PMPCFG0-3, PMPADDR0 CSRs for Linux team
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2021-01-29 18:06:36 -05:00 |
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csrsr.sv
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Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
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2021-01-23 10:48:12 -05:00 |
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csru.sv
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Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
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2021-01-23 10:48:12 -05:00 |
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datapath.sv
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Moving data memory to uncore
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2021-01-29 15:37:51 -05:00 |
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dcu.sv
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Adding stalls for memory delays
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2021-01-30 01:43:49 -05:00 |
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decompress.sv
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Fixed c.jr instruction improperly writing ra
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2021-01-28 15:18:23 -05:00 |
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dtim.sv
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Adding stalls for memory delays
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2021-01-30 01:43:49 -05:00 |
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extend.sv
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Repartitioned with Instruction Fetch Unit, Integer Execution Unit
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2021-01-27 22:49:47 -05:00 |
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flop.sv
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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gpio.sv
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
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hazard.sv
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Adding stalls for memory delays
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2021-01-30 01:43:49 -05:00 |
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ieu.sv
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Moving data memory to uncore
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2021-01-29 15:37:51 -05:00 |
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ifu.sv
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Hint to optimize ifu
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2021-01-28 21:40:48 -05:00 |
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imem.sv
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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mux.sv
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Repartitioned datapath and controller into ieu
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2021-01-27 06:40:26 -05:00 |
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privdec.sv
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Renamed modules in privileged unit
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2021-01-28 23:21:12 -05:00 |
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privileged.sv
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Renamed modules in privileged unit
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2021-01-28 23:21:12 -05:00 |
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regfile.sv
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Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
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2021-01-23 10:48:12 -05:00 |
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shifter.sv
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Replaced parameters with macros for XLEN, MISA, other configuration, and renamed wally-params.sv to wally-config.vh
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2021-01-23 10:48:12 -05:00 |
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subwordread.sv
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Connected AHB bus to Uncore
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2021-01-29 23:43:48 -05:00 |
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subwordwrite.sv
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Connected AHB bus to Uncore
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2021-01-29 23:43:48 -05:00 |
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trap.sv
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Created DCU and moved memdp into DCU
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2021-01-28 01:03:12 -05:00 |
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uart.sv
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
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uartPC16550D.sv
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
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uncore.sv
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
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wallypipelinedhart.sv
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Working on reading instruction from TIM
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2021-01-30 01:57:51 -05:00 |
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wallypipelinedsoc.sv
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Added HCLK and HRESETn
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2021-01-30 00:56:12 -05:00 |
