Reorganized src hierarchically

wally-pipelined/lint-wally

@@ -1,7 +1,7 @@
 # check for warnings in Verilog code
 # The verilator lint tool is faster and better than Modelsim so it is best to run this first.
 
-verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*.sv
+verilator --lint-only --top-module wallypipelinedsoc -Iconfig/rv64ic src/*/*.sv
 
 # --lint-only just runs lint rather than trying to compile and simulate
 # -I points to the include directory where files such as `include wally-config.vh  are found

wally-pipelined/regression/wally-pipelined-batch.do

@@ -27,8 +27,7 @@ vlib work
 # suppress spurious warnngs about 
 # "Extra checking for conflicts with always_comb done at vopt time"
 # because vsim will run vopt
-#vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583
-vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583
+vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583
 
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals

wally-pipelined/regression/wally-pipelined.do

@@ -30,8 +30,8 @@ vlib work
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined.do ../config/rv32ic
 switch $argc {
-    0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583}
-    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*.sv -suppress 2583}
+    0 {vlog +incdir+../config/rv64ic ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
+    1 {vlog +incdir+$1 ../testbench/testbench-imperas.sv ../src/*/*.sv -suppress 2583}
 }
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
@@ -44,6 +44,17 @@ view wave
 # Diplays All Signals recursively
 add wave /testbench/clk
 add wave /testbench/reset
+add wave -divider
+add wave /testbench/dut/hart/ebu/IReadF
+add wave /testbench/dut/hart/DataStall
+add wave /testbench/dut/hart/InstrStall
+add wave /testbench/dut/hart/StallF
+add wave /testbench/dut/hart/StallD
+add wave /testbench/dut/hart/FlushD
+add wave /testbench/dut/hart/FlushE
+add wave /testbench/dut/hart/FlushM
+add wave /testbench/dut/hart/FlushW
+
 add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCF
 add wave -hex /testbench/dut/hart/ifu/InstrF

wally-pipelined/src/uncore/dtim.sv

@@ -77,6 +77,7 @@ module dtim (
       assign #2 entry = HADDR[17:2]; 
   endgenerate
   assign HREADTim = RAM[entry];
+//  assign HREADTim = HREADYTim ? RAM[entry] : ~RAM[entry]; // *** temproary mess up read value before ready
 
   // write each byte based on the byte mask
   // UInstantiate a byte-writable memory here if possible

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -96,13 +96,12 @@ module wallypipelinedhart (
   dcu dcu(/*.Funct3M(InstrM[14:12]),*/ .*); // data cache unit
 
   ahblite ebu( // *** make IRData InstrF
-    .IPAdrF(PCF), .IReadF(1'b0), .IRData(), //.IReady(), 
+    .IPAdrF(PCF), .IReadF(1'b1), .IRData(), //.IReady(), 
     .DPAdrM(DataAdrM), .DReadM(MemRWdcuoutM[1]), .DWriteM(MemRWdcuoutM[0]), .DWDataM(WriteDataM), 
     .DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(), 
     .UnsignedLoadM(Funct3M[2]),
     .*);
   //assign InstrF = ReadDataM[31:0];
-//  assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu
 
 /*  
   mdu mdu(.*); // multiply and divide unit

wally-pipelined/testbench/testbench-imperas.sv

@@ -75,6 +75,7 @@ string tests64iNOc[] = {
                      "rv64i/I-MISALIGN_JMP-01","2000"
   };
  string tests64i[] = '{                 
+                     "rv64i/I-LW-01", "4110",
                      "rv64i/I-ADD-01", "3000",
                      "rv64i/I-ADDI-01", "3000",
                      "rv64i/I-ADDIW-01", "3000",