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Created DCU and moved memdp into DCU

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This commit is contained in:
David Harris 2021-01-28 01:03:12 -05:00
parent be1d1886a9
commit f95d0690ca
8 changed files with 82 additions and 44 deletions
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16
wally-pipelined/src/datapath.sv
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@ -45,18 +45,12 @@ module datapath (
output logic [`XLEN-1:0] PCTargetE,
// Memory stage signals
input logic FlushM,
input logic [1:0] MemRWM,
input logic [2:0] Funct3M,
output logic [`XLEN-1:0] SrcAM,
input logic [`XLEN-1:0] CSRReadValM,
input logic [`XLEN-1:0] PrivilegedNextPCM,
output logic [`XLEN-1:0] WriteDataM, ALUResultM,
input logic [`XLEN-1:0] ReadDataM,
output logic [7:0] ByteMaskM,
output logic [`XLEN-1:0] WriteDataFullM, DataAdrM,
input logic [`XLEN-1:0] ReadDataExtM,
input logic RetM, TrapM,
input logic DataAccessFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM, // *** eventually move these to the memory interface, along with memdp
output logic StoreMisalignedFaultM, StoreAccessFaultM,
// Writeback stage signals
input logic FlushW,
input logic RegWriteW,
@ -80,8 +74,7 @@ module datapath (
logic [`XLEN-1:0] WriteDataE;
logic [`XLEN-1:0] TargetBaseE;
// Memory stage signals
logic [`XLEN-1:0] ReadDataExtM;
logic [`XLEN-1:0] WriteDataFullM;
logic [`XLEN-1:0] ALUResultM;
// Writeback stage signals
logic [`XLEN-1:0] ALUResultW;
logic [`XLEN-1:0] ReadDataW;
@ -114,11 +107,10 @@ module datapath (
// Memory stage pipeline register
floprc #(`XLEN) SrcAMReg(clk, reset, FlushM, SrcAE, SrcAM);
floprc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ALUResultE, ALUResultM);
assign DataAdrM = ALUResultM;
floprc #(`XLEN) WriteDataMReg(clk, reset, FlushM, WriteDataE, WriteDataFullM);
floprc #(5) RdMEg(clk, reset, FlushM, RdE, RdM);
memdp memdp(.AdrM(ALUResultM), .*);
// Writeback stage pipeline register and logic
floprc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ALUResultM, ALUResultW);
floprc #(`XLEN) ReadDataWReg(clk, reset, FlushW, ReadDataExtM, ReadDataW);

47
wally-pipelined/src/dcu.sv Normal file
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@ -0,0 +1,47 @@
///////////////////////////////////////////
// dcu.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Data cache unit
// Top level of the memory-stage hart logic
// Contains data cache, subword read/write datapath, interface to external bus
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module dcu (
input logic [1:0] MemRWM,
input logic [`XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] DataAdrM,
input logic [2:0] Funct3M,
output logic [`XLEN-1:0] ReadDataExtM,
input logic [`XLEN-1:0] WriteDataFullM,
output logic [`XLEN-1:0] WriteDataM,
output logic [7:0] ByteMaskM,
input logic DataAccessFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM,
output logic StoreMisalignedFaultM, StoreAccessFaultM
);
memdp memdp(.*);
endmodule

8
wally-pipelined/src/ieu.sv
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@ -28,9 +28,8 @@
module ieu (
input logic clk, reset,
output logic [1:0] MemRWM,
output logic [7:0] ByteMaskM,
output logic [`XLEN-1:0] ALUResultM, WriteDataM,
input logic [`XLEN-1:0] ReadDataM,
output logic [`XLEN-1:0] DataAdrM, WriteDataFullM,
input logic [`XLEN-1:0] ReadDataExtM,
input logic DataAccessFaultM,
input logic [1:0] ForwardAE, ForwardBE,
input logic StallD, FlushD, FlushE, FlushM, FlushW,
@ -45,9 +44,6 @@ module ieu (
input logic [31:0] InstrD,
input logic [`XLEN-1:0] PCE, PCLinkW,
input logic [`XLEN-1:0] CSRReadValM,
input logic [`XLEN-1:0] PrivilegedNextPCM, // *** eventually move to ifu
output logic LoadMisalignedFaultM, LoadAccessFaultM, // *** eventually move these to the memory interface, along with memdp
output logic StoreMisalignedFaultM, StoreAccessFaultM,
input logic IllegalIEUInstrFaultD,
output logic IllegalBaseInstrFaultD,
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,

35
wally-pipelined/src/memdp.sv
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@ -28,7 +28,7 @@
module memdp (
input logic [1:0] MemRWM,
input logic [`XLEN-1:0] ReadDataM,
input logic [`XLEN-1:0] AdrM,
input logic [`XLEN-1:0] DataAdrM,
input logic [2:0] Funct3M,
output logic [`XLEN-1:0] ReadDataExtM,
input logic [`XLEN-1:0] WriteDataFullM,
@ -36,7 +36,8 @@ module memdp (
output logic [7:0] ByteMaskM,
input logic DataAccessFaultM,
output logic LoadMisalignedFaultM, LoadAccessFaultM,
output logic StoreMisalignedFaultM, StoreAccessFaultM);
output logic StoreMisalignedFaultM, StoreAccessFaultM
);
logic [7:0] bytM;
logic [15:0] HalfwordM;
@ -46,7 +47,7 @@ module memdp (
if (`XLEN == 64) begin
// bytMe mux
always_comb
case(AdrM[2:0])
case(DataAdrM[2:0])
3'b000: bytM = ReadDataM[7:0];
3'b001: bytM = ReadDataM[15:8];
3'b010: bytM = ReadDataM[23:16];
@ -59,7 +60,7 @@ module memdp (
// halfword mux
always_comb
case(AdrM[2:1])
case(DataAdrM[2:1])
2'b00: HalfwordM = ReadDataM[15:0];
2'b01: HalfwordM = ReadDataM[31:16];
2'b10: HalfwordM = ReadDataM[47:32];
@ -69,7 +70,7 @@ module memdp (
logic [31:0] word;
always_comb
case(AdrM[2])
case(DataAdrM[2])
1'b0: word = ReadDataM[31:0];
1'b1: word = ReadDataM[63:32];
endcase
@ -93,14 +94,14 @@ module memdp (
always_comb
if (StoreMisalignedFaultM || StoreAccessFaultM) ByteMaskM = 8'b00000000; // discard Unaligned stores
else case(Funct3M)
3'b000: begin ByteMaskM = 8'b00000000; ByteMaskM[AdrM[2:0]] = 1; end // sb
3'b001: case (AdrM[2:1])
3'b000: begin ByteMaskM = 8'b00000000; ByteMaskM[DataAdrM[2:0]] = 1; end // sb
3'b001: case (DataAdrM[2:1])
2'b00: ByteMaskM = 8'b00000011;
2'b01: ByteMaskM = 8'b00001100;
2'b10: ByteMaskM = 8'b00110000;
2'b11: ByteMaskM = 8'b11000000;
endcase
3'b010: if (AdrM[2]) ByteMaskM = 8'b11110000;
3'b010: if (DataAdrM[2]) ByteMaskM = 8'b11110000;
else ByteMaskM = 8'b00001111;
3'b011: ByteMaskM = 8'b11111111;
default: ByteMaskM = 8'b00000000;
@ -119,7 +120,7 @@ module memdp (
end else begin // 32-bit
// byte mux
always_comb
case(AdrM[1:0])
case(DataAdrM[1:0])
2'b00: bytM = ReadDataM[7:0];
2'b01: bytM = ReadDataM[15:8];
2'b10: bytM = ReadDataM[23:16];
@ -128,7 +129,7 @@ module memdp (
// halfword mux
always_comb
case(AdrM[1])
case(DataAdrM[1])
1'b0: HalfwordM = ReadDataM[15:0];
1'b1: HalfwordM = ReadDataM[31:16];
endcase
@ -150,8 +151,8 @@ module memdp (
always_comb
if (StoreMisalignedFaultM || StoreAccessFaultM) ByteMaskM = 8'b0000; // discard Unaligned stores
else case(Funct3M)
3'b000: begin ByteMaskM = 8'b0000; ByteMaskM[{1'b0,AdrM[1:0]}] = 1; end // sb
3'b001: if (AdrM[1]) ByteMaskM = 8'b1100;
3'b000: begin ByteMaskM = 8'b0000; ByteMaskM[{1'b0,DataAdrM[1:0]}] = 1; end // sb
3'b001: if (DataAdrM[1]) ByteMaskM = 8'b1100;
else ByteMaskM = 8'b0011;
3'b010: ByteMaskM = 8'b1111;
default: ByteMaskM = 8'b0000;
@ -172,12 +173,12 @@ module memdp (
always_comb
case(Funct3M)
3'b000: UnalignedM = 0; // lb, sb
3'b001: UnalignedM = AdrM[0]; // lh, sh
3'b010: UnalignedM = AdrM[1] | AdrM[0]; // lw, sw, flw, fsw
3'b011: UnalignedM = |AdrM[2:0]; // ld, sd, fld, fsd
3'b001: UnalignedM = DataAdrM[0]; // lh, sh
3'b010: UnalignedM = DataAdrM[1] | DataAdrM[0]; // lw, sw, flw, fsw
3'b011: UnalignedM = |DataAdrM[2:0]; // ld, sd, fld, fsd
3'b100: UnalignedM = 0; // lbu
3'b101: UnalignedM = AdrM[0]; // lhu
3'b110: UnalignedM = |AdrM[1:0]; // lwu
3'b101: UnalignedM = DataAdrM[0]; // lhu
3'b110: UnalignedM = |DataAdrM[1:0]; // lwu
default: UnalignedM = 0;
endcase

2
wally-pipelined/src/privileged.sv
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@ -41,7 +41,7 @@ module privileged (
input logic LoadMisalignedFaultM, LoadAccessFaultM,
input logic StoreMisalignedFaultM, StoreAccessFaultM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, DataAdrM,
input logic [4:0] SetFflagsM,
output logic [2:0] FRM_REGW,
input logic FlushD, FlushE, FlushM, StallD

10
wally-pipelined/src/trap.sv
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@ -37,7 +37,7 @@ module trap (
input logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW,
input logic [11:0] MIP_REGW, MIE_REGW,
input logic STATUS_MIE, STATUS_SIE,
input logic [`XLEN-1:0] InstrMisalignedAdrM, ALUResultM,
input logic [`XLEN-1:0] InstrMisalignedAdrM, DataAdrM,
input logic [31:0] InstrM,
output logic TrapM, MTrapM, STrapM, UTrapM, RetM,
output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
@ -107,11 +107,11 @@ module trap (
always_comb
if (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
else if (LoadMisalignedFaultM) NextFaultMtvalM = ALUResultM;
else if (StoreMisalignedFaultM) NextFaultMtvalM = ALUResultM;
else if (LoadMisalignedFaultM) NextFaultMtvalM = DataAdrM;
else if (StoreMisalignedFaultM) NextFaultMtvalM = DataAdrM;
else if (InstrPageFaultM) NextFaultMtvalM = 0; // *** implement
else if (LoadPageFaultM) NextFaultMtvalM = ALUResultM;
else if (StorePageFaultM) NextFaultMtvalM = ALUResultM;
else if (LoadPageFaultM) NextFaultMtvalM = DataAdrM;
else if (StorePageFaultM) NextFaultMtvalM = DataAdrM;
else if (IllegalInstrFaultM) NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
else NextFaultMtvalM = 0;
endmodule

2
wally-pipelined/src/wallypipelined.sv
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@ -70,7 +70,7 @@ module wallypipelined (
logic ExtIntM = 0; // not yet connected
// instantiate processor and memories
wallypipelinedhart hart(.ALUResultM(DataAdrM), .*);
wallypipelinedhart hart(.*);
imem imem(.AdrF(PCF[`XLEN-1:1]), .*);
dmem dmem(.AdrM(DataAdrM), .*);

6
wally-pipelined/src/wallypipelinedhart.sv
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@ -32,7 +32,7 @@ module wallypipelinedhart (
input logic [31:0] InstrF,
output logic [1:0] MemRWM,
output logic [7:0] ByteMaskM,
output logic [`XLEN-1:0] ALUResultM, WriteDataM,
output logic [`XLEN-1:0] DataAdrM, WriteDataM,
input logic [`XLEN-1:0] ReadDataM,
input logic TimerIntM, ExtIntM, SwIntM,
input logic InstrAccessFaultF,
@ -50,6 +50,7 @@ module wallypipelinedhart (
logic [`XLEN-1:0] PCTargetE;
logic [`XLEN-1:0] CSRReadValM;
logic [`XLEN-1:0] PrivilegedNextPCM;
logic [`XLEN-1:0] ReadDataExtM, WriteDataFullM;
logic InstrValidW;
logic InstrMisalignedFaultM;
logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
@ -72,7 +73,8 @@ module wallypipelinedhart (
ifu ifu(.*); // instruction fetch unit: PC, branch prediction, instruction cache
ieu ieu(.*); // inteber execution unit: integer register file, datapath and controller
// dcu dcu(.*); // data cache unit
dcu dcu(.Funct3M(InstrM[14:12]), .*); // data cache unit
/*
mdu mdu(.*); // multiply and divide unit
fpu fpu(.*); // floating point unit