cvw/wally-pipelined/src
2021-04-22 01:51:38 -04:00
..
cache Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
dmem Implement virtual memory protection 2021-04-21 19:58:36 -04:00
ebu Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
fpu Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
generic change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
hazard Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
ieu Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
ifu Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-21 20:01:08 -04:00
mmu Implement virtual memory protection 2021-04-21 19:58:36 -04:00
muldiv Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
privileged Fix misa bug 2021-04-22 00:59:07 -04:00
uncore working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
wally Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00