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Moved LoadStall generation to IEU

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This commit is contained in:
David Harris 2021-02-02 13:42:23 -05:00
parent aad1d3d7dd
commit c23afbda3a
4 changed files with 77 additions and 37 deletions
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47
wally-pipelined/src/hazard/hazard.sv
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@ -30,25 +30,14 @@ module hazard(
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
input logic PCSrcE, MemReadE,
input logic RegWriteM, RegWriteW, CSRWritePendingDEM, RetM, TrapM,
input logic LoadStallD,
input logic InstrStall, DataStall,
// Forwaring controls
output logic [1:0] ForwardAE, ForwardBE,
// Stall outputs
output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW,
output logic LoadStallD);
// forwarding logic
always_comb begin
ForwardAE = 2'b00;
ForwardBE = 2'b00;
if (Rs1E != 5'b0)
if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
if (Rs2E != 5'b0)
if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
end
output logic StallF, StallD, FlushD, FlushE, FlushM, FlushW
);
logic BranchFlushDE;
logic StallDCause, StallFCause, StallWCause;
// stalls and flushes
// loads: stall for one cycle if the subsequent instruction depends on the load
@ -62,20 +51,16 @@ module hazard(
// A stage must stall if the next stage is stalled
// If any stages are stalled, the first stage that isn't stalled must flush.
assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
assign StallD = LoadStallD;
assign StallF = StallD | InstrStall | CSRWritePendingDEM;
assign FlushD = PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
assign FlushE = LoadStallD | PCSrcE | RetM | TrapM;
assign BranchFlushDE = PCSrcE | RetM | TrapM;
assign StallDCause = LoadStallD;
assign StallFCause = InstrStall | CSRWritePendingDEM;
assign StallWCause = DataStall; // *** not yet used
assign StallD = StallDCause;
assign StallF = StallD | StallFCause;
assign FlushD = BranchFlushDE | StallFCause; // PCSrcE |InstrStall | CSRWritePendingDEM | RetM | TrapM;
assign FlushE = StallD | BranchFlushDE; //LoadStallD | PCSrcE | RetM | TrapM;
assign FlushM = RetM | TrapM;
assign FlushW = TrapM;
/*
assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
assign StallD = LoadStallD;
assign StallF = StallD | CSRWritePendingDEM;
assign FlushD = PCSrcE | CSRWritePendingDEM | RetM | TrapM;
assign FlushE = LoadStallD | PCSrcE | RetM | TrapM;
assign FlushM = RetM | TrapM;
assign FlushW = TrapM; */
endmodule

2
wally-pipelined/src/ieu/datapath.sv
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@ -56,7 +56,7 @@ module datapath (
input logic [`XLEN-1:0] PCLinkW,
// Hazard Unit signals
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E,
output logic [4:0] RdE, RdM, RdW
output logic [4:0] RdE, RdM, RdW
);
// Fetch stage signals

52
wally-pipelined/src/ieu/forward.sv Normal file
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@ -0,0 +1,52 @@
///////////////////////////////////////////
// forward.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: Determine datapath forwarding
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module forward(
// Detect hazards
input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
input logic MemReadE,
input logic RegWriteM, RegWriteW,
// Forwaring controls
output logic [1:0] ForwardAE, ForwardBE,
output logic LoadStallD
);
always_comb begin
ForwardAE = 2'b00;
ForwardBE = 2'b00;
if (Rs1E != 5'b0)
if ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
if (Rs2E != 5'b0)
if ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
end
assign LoadStallD = MemReadE & ((Rs1D == RdE) | (Rs2D == RdE));
endmodule

13
wally-pipelined/src/ieu/ieu.sv
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@ -48,12 +48,10 @@ module ieu (
output logic InstrValidW,
// hazards
input logic StallD, FlushD, FlushE, FlushM, FlushW,
input logic LoadStallD,
input logic [1:0] ForwardAE, ForwardBE,
input logic RetM, TrapM,
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
output logic LoadStallD,
output logic PCSrcE,
output logic MemReadE,
// output logic MemReadE,
output logic RegWriteM,
output logic RegWriteW,
output logic CSRWriteM, PrivilegedM,
@ -65,10 +63,15 @@ module ieu (
logic [4:0] ALUControlE;
logic ALUSrcAE, ALUSrcBE;
logic [1:0] ResultSrcW;
logic TargetSrcE;
// forwarding signals
logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW;
logic [1:0] ForwardAE, ForwardBE;
logic MemReadE;
controller c(.OpD(InstrD[6:0]), .Funct3D(InstrD[14:12]), .Funct7b5D(InstrD[30]), .*);
datapath dp(.*);
forward fw(.*);
endmodule