forked from Github_Repos/cvw
Working on reading instruction from TIM
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@ -44,6 +44,7 @@ module ahblite (
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input logic DReadM, DWriteM,
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input logic [`XLEN-1:0] DWDataM,
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input logic [1:0] DSizeM,
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// Return from bus
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output logic [`XLEN-1:0] DRData,
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// output logic DReady,
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// AHB-Lite external signals
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@ -55,6 +55,7 @@ module wallypipelinedhart (
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// new signals that must connect through DP
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logic CSRWriteM, PrivilegedM;
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logic [`XLEN-1:0] SrcAM;
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// logic [31:0] InstrF;
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logic [31:0] InstrD, InstrM;
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logic [`XLEN-1:0] PCE, PCM, PCLinkW;
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logic [`XLEN-1:0] PCTargetE;
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@ -100,6 +101,7 @@ module wallypipelinedhart (
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.DSizeM(Funct3M[1:0]), .DRData(ReadDataM), //.DReady(),
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.UnsignedLoadM(Funct3M[2]),
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.*);
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//assign InstrF = ReadDataM[31:0];
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// assign UnsignedLoadM = Funct3M[2]; // *** maybe move read extension to dcu
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/*
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