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1014 Commits

Author SHA1 Message Date
bbracker
c643372e1d merge conflict resolved -- Ross and I made the same fix 2021-05-03 10:10:42 -04:00
bbracker
9ab714e636 small rv64 plic test bugfix 2021-05-03 10:06:44 -04:00
Ross Thompson
c7b97d0339 Added back in function name to wave.do 2021-05-03 09:04:48 -05:00
Ross Thompson
c0a4b7cb17 Fixed typo in ifu for bypassing branch predictor. 
Fixed missing signal name in local history predictor.
 2021-05-03 08:56:45 -05:00
David Harris
a37d9b5e8e Fixed lint error in div 2021-05-03 09:26:12 -04:00
bbracker
9bde239143 ifu lint fixes 2021-05-03 09:25:22 -04:00
bbracker
2368b58cc9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-05-03 09:23:52 -04:00
Noah Boorstin
b32128465c busybear: remove now unneeded hack for fixed CSR issue 2021-05-01 15:17:04 -04:00
Katherine Parry
db95151d8d fpu imperas tests run 2021-05-01 02:18:01 +00:00
bbracker
1fcd43e844 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-30 06:26:35 -04:00
bbracker
182bfdbb0e rv32 plic test and lint fixes 2021-04-30 06:26:31 -04:00
Noah Boorstin
48d32c1daf rollback regression to 400k instrs for busybear 2021-04-29 20:59:30 -04:00
Domenico Ottolia
d03ca20dc9 Make vectored interrupt trap handling work, and add tests for mtvec with vectored interrupts 2021-04-29 20:42:14 -04:00
Ross Thompson
818c0abc89 Fixed memory size in configs for rv32ic and rv64ic. 
Removed warning on call to $fscanf.
 2021-04-29 17:36:46 -05:00
Domenico Ottolia
c60c4f4adc Minor improvements to scause test 2021-04-29 16:48:07 -04:00
Domenico Ottolia
c8a81779ca Add machine-mode timer interrupts to mcause tests 2021-04-29 16:39:18 -04:00
Thomas Fleming
6e5fc107d9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-29 16:30:00 -04:00
Domenico Ottolia
6fc04768f5 Same but don't break sim-wally this time 2021-04-29 15:33:27 -04:00
Domenico Ottolia
7ae5d4d11e Add more exceptions to medeleg tests 2021-04-29 15:32:13 -04:00
ushakya22
9dfbfd5772 fix to pcm bug 2021-04-29 15:21:08 -04:00
ushakya22
77210527c1 Working MIE timer tests 2021-04-29 15:19:43 -04:00
Domenico Ottolia
4fae8088e3 Add medeleg tests 2021-04-29 15:02:36 -04:00
Jarred Allen
bf54c9b0b2 Enhance lint-wally functionality 2021-04-29 14:48:41 -04:00
Jarred Allen
ebd9c0ee29 Remove signal which no longer exists from default waves, so sim-wally works 2021-04-29 14:41:10 -04:00
Jarred Allen
8fd9cc679b Fix compile error in branch predictor 2021-04-29 14:36:56 -04:00
Shreya Sanghai
1e57c6bb92 fixed bug in gshare, global and local history BP 2021-04-29 06:14:32 -04:00
Thomas Fleming
5f2bccd88f Clean up PMA checker and begin PMP checker 2021-04-29 02:20:39 -04:00
Thomas Fleming
c62fdfb7b3 Remove unused waves from .do files 2021-04-29 02:19:46 -04:00
Thomas Fleming
18e0b353a9 Add mmu waves (commented) to busybear 2021-04-28 20:01:05 -04:00
Noah Boorstin
a4dad3403e same but do that right this time 2021-04-28 14:27:28 -04:00
Domenico Ottolia
60dc6aaf48 Modify make file to make privileged tests always pass Imperas (for testing interrupts) & Add mtvec/stvec tests 2021-04-27 21:47:38 -04:00
Noah Boorstin
44606b6c19 busybear: respect branch predictor disable config 2021-04-27 15:52:18 -04:00
Ross Thompson
8ae28e7887 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-26 14:28:09 -05:00
Ross Thompson
72363f5c66 Added the ability to exclude branch predictor. 2021-04-26 14:27:42 -05:00
Noah Boorstin
ff1a6b63ed ok but do that better 2021-04-26 14:38:05 -04:00
Noah Boorstin
0324329ed9 linux: start using internal branch predictor signal 2021-04-26 14:34:38 -04:00
Ross Thompson
afbb100860 Fixed issue with not saving the first cache block read on a miss spill. 2021-04-26 12:57:34 -05:00
Noah Boorstin
ee628e388a minor busybear fixes 2021-04-26 13:24:39 -04:00
Ross Thompson
8e5409af66 Icache integrated! 
Merge branch 'icache-almost-working' into main
 2021-04-26 11:48:58 -05:00
Ross Thompson
467a463c13 Reverted back the exe2memfile.pl script changes. Something I changed broke the load tests. 2021-04-26 10:44:27 -05:00
bbracker
31a0387136 merge cleanup; mem init is broken 2021-04-26 08:00:17 -04:00
bbracker
ba94fa3436 it says I need to merge in order to pull 2021-04-26 07:46:24 -04:00
bbracker
1cc0dcc83f progress on bus and lrsc 2021-04-26 07:43:16 -04:00
Ross Thompson
6e803b724e Merge branch 'tests' into icache-almost-working 2021-04-25 21:25:36 -05:00
bbracker
86946266cf thomas fixed it before I did 2021-04-24 09:38:52 -04:00
bbracker
a3487a9e47 do script refactor 2021-04-24 09:32:09 -04:00
Thomas Fleming
c21bd8a463 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-23 20:12:27 -04:00
Thomas Fleming
e3672ca23f Add address translation to busybear testbench 2021-04-23 20:12:20 -04:00
Thomas Fleming
288a6d82ce Fix HSIZE and HBURST signal widths in PMA checker 2021-04-23 20:11:43 -04:00
David Harris
85eb6bcf1a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-23 19:04:29 -04:00
David Harris
9415e00bfa Fixed exe2memfile.pl to handle large files 2021-04-23 19:04:16 -04:00
Ross Thompson
27ef10df07 almost working icache. 2021-04-23 16:47:23 -05:00
Noah Boorstin
09755251bc busybear 2021-04-23 17:32:37 -04:00
Shriya Nadgauda
c66e63ff70 adding pipeline testing 2021-04-23 14:19:17 -04:00
Jarred Allen
c91f1e197b Remind people to run make allclean when a regression fails 2021-04-22 19:21:00 -04:00
Ross Thompson
020fb65adf Fixed icache for 32 bit. 
Merge branch 'cache' into main
 2021-04-22 16:45:29 -05:00
Ross Thompson
c42399bdb5 Yes. The hack to not repeat the d memory operation fixed this issue. 2021-04-22 15:22:56 -05:00
Thomas Fleming
da76b80991 Write PCM to TVAL registers 2021-04-22 16:17:57 -04:00
Thomas Fleming
8fee3b3872 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 15:37:19 -04:00
Thomas Fleming
00ce24e67c Prepare to squash bad ahb accesses 2021-04-22 15:36:45 -04:00
Thomas Fleming
53c05d6a73 Clean up lint errors in fpu and muldiv 
booth.sv had an actual error where a signal was being assigned to too
many bits. muldiv has a lot of non blocking assignments, so I suppressed
those warnings so the linter output was readable.
 2021-04-22 15:36:03 -04:00
Domenico Ottolia
6b4d2e9634 Fix misa synthesis bug (for real now) 2021-04-22 15:35:20 -04:00
Thomas Fleming
38236e9172 Implement first pass at the PMA checker 2021-04-22 15:34:02 -04:00
Thomas Fleming
73d9e7775c Pass lint-wally arguments to verilator 2021-04-22 13:39:20 -04:00
Jarred Allen
5df6be3ad5 Add buildroot to regression test 2021-04-22 13:34:56 -04:00
Thomas Fleming
6d1a6694a8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-22 13:20:12 -04:00
Thomas Fleming
6acaa313b5 Temporarily disable rv64 mmu test 
Will restore once cache revamp is pushed
 2021-04-22 13:19:18 -04:00
bbracker
74b35ac57a greatly improved PLIC register interface 2021-04-22 11:22:01 -04:00
Ross Thompson
d8ab7a5de2 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
00b3e36b30 Refactor tlb_ram to use flop primitives 2021-04-22 01:52:43 -04:00
Thomas Fleming
ef80176e2c Extend stall on leaf page lookups 2021-04-22 01:51:38 -04:00
Domenico Ottolia
fb8f244dab Fix misa bug 2021-04-22 00:59:07 -04:00
Thomas Fleming
e336fbd108 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
4bae666fa1 Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Ross Thompson
7b3735fc25 Fixed for the instruction spills. 2021-04-21 16:47:05 -05:00
Teo Ene
c7a21b05f7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-21 16:06:33 -05:00
Teo Ene
ddc98e7d08 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Noah Boorstin
cd7ea29ce6 buildroot: add workaround for weird initial MSTATUS state 2021-04-21 16:03:42 -04:00
Ross Thompson
532c8771ba major progress. 
It's running the icache is imperas tests now.
Compressed does not work yet.
 2021-04-21 08:39:54 -05:00
Domenico Ottolia
44da1488ff Add tests for stval and mtval 2021-04-21 02:31:32 -04:00
Domenico Ottolia
f63f16f486 Add tests for scause, and improve tests for sepc. Also make improvements to privileged test generator run.sh file 2021-04-21 01:12:55 -04:00
Domenico Ottolia
bf86a809eb Add tests for sepc register 2021-04-20 23:50:53 -04:00
Ross Thompson
f3093ac612 Why was the linter messed up? 
There are a number of combo loops which need fixing outside the icache.  They may be fixed in main.
We get to instruction address 50 now!
 2021-04-20 22:06:12 -05:00
Ross Thompson
99424fb983 Progress on icache. Fixed some issues aligning the PC with instruction. Still broken. 2021-04-20 21:19:53 -05:00
Ross Thompson
251ece20fe Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Domenico Ottolia
0c307d2db1 Fix synthesis warnings for privileged unit (replace 'initial' settings) 2021-04-20 17:57:56 -04:00
Noah Boorstin
3f0ead9d4e yay buildroot passes a decent amount of tests now 
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
 2021-04-19 03:26:08 -04:00
Jarred Allen
850f728cc7 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Katherine Parry
d12eb0f4eb fixed synth bugs in fpu 2021-04-19 00:39:16 +00:00
Noah Boorstin
2af4e2f4ac slowly more buildroot progress 2021-04-18 18:18:07 -04:00
Noah Boorstin
9bb1233433 neat verilog thing 2021-04-18 17:48:51 -04:00
Noah Boorstin
6954e6df4c buildroot: sim is now running! 
yes it only gets through 5 instructions right now. Yes that's my fault.
 2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761 start to add buildroot testbench 
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
 2021-04-16 23:27:29 -04:00
Jarred Allen
aef57cab50 dcache lints 2021-04-15 21:13:56 -04:00
Jarred Allen
7854d838c7 Enable linting of blocks not yet in the hierarchy 2021-04-15 21:13:40 -04:00
bbracker
290b3424e5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 21:09:27 -04:00
bbracker
368c94d4ff working GPIO interrupt demo 2021-04-15 21:09:15 -04:00
Domenico Ottolia
9f13ee3f31 Add tests for scause and ucause 2021-04-15 19:41:25 -04:00
Domenico Ottolia
92bb38fa8c Add support for vectored interrupts 2021-04-15 19:13:42 -04:00
Domenico Ottolia
eb9e1843fc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 16:57:27 -04:00
Domenico Ottolia
531423d7e1 Add 32 bit privileged tests 2021-04-15 16:55:39 -04:00
Teo Ene
2814579f30 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-15 15:29:09 -05:00
Teo Ene
374a93dae6 Quick fix to ahblite missing default statement done in class :) 2021-04-15 15:29:04 -05:00
Thomas Fleming
e780694ee0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/mmu/priority_encoder.sv
 2021-04-15 16:20:43 -04:00
Thomas Fleming
6dd7591ceb Change priority encoder to avoid extra assignment 2021-04-15 16:17:35 -04:00
Thomas Fleming
ff9f1e5e72 Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Teo Ene
ad86295fcf Temporary change to mmu/priority_encoder.sv 
Necessary to get synth working
Original HDL is still there, just commented out
 2021-04-15 13:37:12 -05:00
Katherine Parry
636e2de9df integraded the FMA into the FPU 2021-04-15 18:28:00 +00:00
Jarred Allen
81c02bda55 Merge branch 'main' into cache 2021-04-15 13:47:19 -04:00
Ross Thompson
87b716170c Merge branch 'bpfixes' into main 2021-04-15 09:06:21 -05:00
Shreya Sanghai
0369fc5d1e Cherry Pick merge of Shreya's localhistory predictor changes into main. 
fixed minor bugs in localHistory
 2021-04-15 09:04:36 -05:00
ShreyaSanghai
6d4042e479 added localHistoryPredictor 2021-04-15 08:58:22 -05:00
Shreya Sanghai
7e9a0602ea fixed bugs in global history to read latest GHRE 
Cherry pick Shreya's commits into main branch.
 2021-04-15 08:55:22 -05:00
bbracker
e69cc0d23a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-15 09:06:03 -04:00
bbracker
51cdff3e9b csri lint improvement 2021-04-15 09:05:53 -04:00
Jarred Allen
3717699ad9 Add a comment to explain a detail 2021-04-14 23:14:59 -04:00
Thomas Fleming
3c49fd08f6 Remove imem from testbenches 2021-04-14 20:20:34 -04:00
Jarred Allen
892dfd5a9b More icache bugfixes 2021-04-14 19:03:33 -04:00
Jarred Allen
c1e2e58ebe Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/cache/dmapped.sv
	wally-pipelined/src/cache/line.sv
	wally-pipelined/src/ifu/icache.sv
 2021-04-14 18:24:32 -04:00
bbracker
8f7ddcfdff rv64 interrupt servicing 2021-04-14 10:19:42 -04:00
Noah Boorstin
d66fcbc4ab busybear: use (slightly) less terrible verilog 2021-04-14 00:18:44 -04:00
Noah Boorstin
c75455cc41 busybear testbench updates 
start speculative checking on CSR* satp, *
add some slight delays in some CSR checkings to make them deterministic

I realize this verilog is incredibly un-idiomatic. But I still don't
know of anything better. If you figure it out, please let me know
 2021-04-14 00:00:27 -04:00
Thomas Fleming
7d2d6823f1 Fix mmu lint errors 2021-04-13 19:19:58 -04:00
Thomas Fleming
0a9b208729 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-13 17:15:10 -04:00
Katherine Parry
ef011496a7 Various bugs fixed in FMA 2021-04-13 18:27:13 +00:00
Thomas Fleming
09c9c49541 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/pagetablewalker.sv
 2021-04-13 13:42:03 -04:00
Thomas Fleming
6188f10732 Move InstrPageFault to fetch stage 2021-04-13 13:39:22 -04:00
Thomas Fleming
dc8a165806 Add lru algorithm to TLB 2021-04-13 13:37:24 -04:00
Teo Ene
1018a10625 Various code syntax changes to bring HDL to a synthesizable level 2021-04-13 11:27:12 -05:00
Jarred Allen
4ae1df1290 Merge branch 'main' into cache 2021-04-13 01:10:03 -04:00
Jarred Allen
fc8b8ad7aa A few more cache fixes 2021-04-13 01:07:40 -04:00
Ross Thompson
35f8b4f74f Fixed minor bug in muldiv which corrects the lint error. 2021-04-09 10:56:31 -05:00
ushakya22
99f2d24e05 Latest IE tests with timer interupts 2021-04-08 17:53:39 -04:00
Jarred Allen
d99b8f772e Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Ross Thompson
e73e16e57a Created special test for driving the instruction spill error. 
The extact problem occurs when a 4 byte instruction startles two cache blocks (or without a cache two ahbi words) and the code jumps to a cache block other than the next cache block. Consider the following sample of code.

0000000000000080 <test_spill>:
  80:	42a9                	li	t0,10
  82:	0001                	nop
  84:	0001                	nop
  86:	0001                	nop
  88:	02bd                	addi	t0,t0,15
  8a:	00628e33          	add	t3,t0,t1
  8e:	01ce8963          	beq	t4,t3,a0 <match>

0000000000000092 <failure>:
  92:	557d                	li	a0,-1
  94:	8082                	ret
  96:	00000013          	nop
  9a:	00000013          	nop
  9e:	0001                	nop

00000000000000a0 <match>:
  a0:	1ffd                	addi	t6,t6,-1
  a2:	fc0f9fe3          	bnez	t6,80 <test_spill>
  a6:	4501                	li	a0,0
  a8:	8082                	ret

Instructions 0x88, 0x8a and 0x8e are read incorrectly.  However once the branch predictor begins to correctly predict the beq at 0x8e the instrution at 0xa0 is loaded incorrectly as the 2 upper bytes of 0x8e and the two bytes of 0x92.  This amalgamation causes c.addi at 0xa0 to do something else and the loop never terminates.

The button of wavefile wave.do shows the exact problem in the 'icache'.
 2021-04-08 15:05:08 -05:00
bbracker
1ee8feffe5 integrated peripheral testing into existing workflow 2021-04-08 15:31:39 -04:00
bbracker
005f838b8d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:28:25 -04:00
bbracker
755e2e5771 merge testbench 2021-04-08 14:28:01 -04:00
Katherine Parry
b7ebfd66ed Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:06:51 +00:00
David Harris
8549e457c1 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 14:04:09 -04:00
David Harris
6b2868a8c7 restored testbench-imperas.sv 2021-04-08 14:04:01 -04:00
Katherine Parry
2ee015d53e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 18:03:57 +00:00
Katherine Parry
f4cb92ae71 fixed FPU lint warnings 2021-04-08 18:03:21 +00:00
Katherine Parry
27cb94e7af fixed FPU lint warnings 2021-04-08 17:55:25 +00:00
ushakya22
72a64edfb8 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-04-08 13:55:23 -04:00
ushakya22
b0f6898ece Updates to WALLY-IE tests 2021-04-08 13:54:42 -04:00
David Harris
ac8a111d61 merge conflict resolution 2021-04-08 13:53:56 -04:00
David Harris
6a6ccca3c8 fixed sim-wally-32ic 2021-04-08 13:40:16 -04:00
Noah Boorstin
14d2ad1e2d try to remove git-lfs stuff 2021-04-08 13:23:11 -04:00
Domenico Ottolia
3067e94b4b Update privileged testgen & helper script 2021-04-08 05:14:07 -04:00
Domenico Ottolia
65abe13f4f Cause an Illegal Instruction Exception when attempting to write readonly CSRs 2021-04-08 05:12:54 -04:00
Thomas Fleming
fc39535e4e Refactor TLB into multiple files 2021-04-08 03:24:10 -04:00
Thomas Fleming
c54aecde73 Provide attribution link for priority encoder 2021-04-08 03:05:06 -04:00
Thomas Fleming
303c2c4839 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
4322694f7a Switch to use RV64IC for the benchmarks. 
Still not working correctly with the icache.

instr
addr   correct   got
 2021-04-07 19:12:43 -05:00
ushakya22
83d9aa3a50 MIE privilege tests with working timer interupt 2021-04-07 04:09:09 -04:00
Domenico Ottolia
60cf38192b Add privileged tests to testbench 2021-04-07 02:22:08 -04:00
Domenico Ottolia
465d3986b0 Add passing mtval and mepc tests 2021-04-07 02:21:05 -04:00
Ross Thompson
c91436d3b7 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Ross Thompson
98a04abe6c Merge remote-tracking branch 'refs/remotes/origin/tests' into tests 2021-04-06 21:20:55 -05:00
Ross Thompson
bff2d61a1f Steps to getting branch predictor benchmarks running. 2021-04-06 21:20:51 -05:00
Jarred Allen
bd8f1eea3c Fix another bug in icache 2021-04-06 17:47:00 -04:00
Jarred Allen
3afc358974 Fix another bug in icache 2021-04-06 12:48:42 -04:00
Noah Boorstin
284d583877 add busybear boot files with git-lfs 2021-04-05 19:38:43 -04:00
Noah Boorstin
0e3f013212 busybear: reenable 'ruthless' CSR checking 2021-04-05 12:53:30 -04:00
bbracker
38017e6aae declare memread signal 2021-04-05 08:13:01 -04:00
bbracker
a4c3afb847 PLIC claim reg side effects now check for memread signal 2021-04-05 08:03:14 -04:00
bbracker
4a5aa5b202 plic subword access compliance 2021-04-04 23:10:33 -04:00
Katherine Parry
e6a7353847 Added missing files in FPU 2021-04-04 18:09:13 +00:00
bbracker
31c6b2d01f Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 06:40:53 -04:00
Thomas Fleming
6b43381c38 Comment out fpu from hart until module exists 2021-04-03 22:34:11 -04:00
Thomas Fleming
dbd5a4320e Merge branch 'mmu' into main 
Conflicts:
	wally-pipelined/src/wally/wallypipelinedhart.sv
 2021-04-03 22:12:52 -04:00
Thomas Fleming
8dfec29f7e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-03 22:09:50 -04:00
Noah Boorstin
f4e5642c62 busybear: temporary stop after 800k instrs 2021-04-03 21:37:57 -04:00
Thomas Fleming
1cbdaf1f05 Fix extraneous page fault stall 2021-04-03 21:28:24 -04:00
Jarred Allen
c95da7d11e Fix bug in icache 2021-04-03 18:10:54 -04:00
Katherine Parry
d7b1379ab8 Integrated FPU 2021-04-03 20:52:26 +00:00
Ross Thompson
d21006d048 Partial fix to the integer divide stall issue. 2021-04-02 15:32:15 -05:00
James E. Stine
362f6ea2e6 Minor cleanup 2021-04-02 08:20:44 -05:00
James E. Stine
0595ae983f Put back imperas testbench until figure out why m_supported is running for rv64ic 2021-04-02 08:19:25 -05:00
James E. Stine
cff08adc3a Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal. 2021-04-02 06:27:37 -05:00
Thomas Fleming
bfb4b051c6 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
38a0199260 Merge branch 'mmu' of github.com:davidharrishmc/riscv-wally into mmu 2021-04-01 16:23:19 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Jarred Allen
5afb255251 Begin changes to direct-mapped cache 2021-04-01 13:55:21 -04:00
Shreya Sanghai
df149d1be7 fixed minor bugs in localHistory 2021-04-01 13:40:08 -04:00
James E. Stine
0495195d68 Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
ShreyaSanghai
28a9c6ba56 added localHistoryPredictor 2021-04-01 22:22:40 +05:30
Shreya Sanghai
b544526766 fixed bugs in global history to read latest GHRE 2021-03-31 21:56:14 -04:00
Teo Ene
7c364a26e9 Updated MISA in coremark_bare config file 2021-03-31 20:39:02 -05:00
Noah Boorstin
75f58c4df5 busybear: temporarially stop checking CSRs 2021-03-31 14:14:32 -04:00
Noah Boorstin
118e846ef7 busybear: clean up questa warnings 2021-03-31 14:04:57 -04:00
Noah Boorstin
43532be770 busybear: clean up questa warnings 2021-03-31 14:02:15 -04:00
Ross Thompson
9172e52286 Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
a64a37d702 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
77b8e27205 Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
56e256baa5 Extend lint-wally to lint both rv32 and rv64 2021-03-30 22:42:28 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
Thomas Fleming
0994d03b28 Update virtual memory tests and move to separate folder 2021-03-30 22:18:29 -04:00
Domenico Ottolia
f7cbaeb217 Add one more test to WALLY-CAUSE, and update privileged testgen 2021-03-30 19:44:58 -04:00
Domenico Ottolia
6619a5f44f Add mcause tests to testbench 2021-03-30 17:17:59 -04:00
Domenico Ottolia
61b19a0cd0 Update privileged tests generator 2021-03-30 16:58:46 -04:00
Domenico Ottolia
351c71e812 Add all working mcause tests 2021-03-30 16:55:12 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
ushakya22
fbed5d658e privilege tests 2021-03-30 15:23:47 -04:00
Ross Thompson
2a308309e4 fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
631454ccf9 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
6e83ccc3c4 Comment out failing tests 2021-03-30 13:07:26 -04:00
Jarred Allen
108f18e580 Merge branch 'cache' into main 2021-03-30 12:56:19 -04:00
Jarred Allen
7ca57cc4fc Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
David Harris
8723fb916c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-26 13:04:52 -04:00
David Harris
637bba6509 Added fp test to testbench 2021-03-26 13:03:23 -04:00
Noah Boorstin
b5a1691c2b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-busybear.sv
 2021-03-26 12:26:30 -04:00
Shreya Sanghai
339bd5d3eb Merge branch 'PPA' into main 
Conflicts:
	wally-pipelined/testbench/testbench-privileged.sv
 2021-03-25 20:35:21 -04:00
Shreya Sanghai
cc988f420f removed minor bugs 2021-03-25 20:29:50 -04:00
Jarred Allen
39bf2347bc Fix error when reading an instruction that crosses a line boundary 2021-03-25 18:47:23 -04:00
ShreyaSanghai
139c2076a1 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
32829bf7a1 Remove old icache 2021-03-25 15:46:35 -04:00
Jarred Allen
5f4feb0ff1 Works for misaligned instructions not on line boundaries 2021-03-25 15:42:17 -04:00
Noah Boorstin
05d362e334 regression: use busybear batch instead 2021-03-25 15:34:10 -04:00
Domenico Ottolia
56a32b5882 More bug fixes for privileged tests 2021-03-25 15:05:55 -04:00
Jarred Allen
3b4f0141f4 Begin work on compressed instructions 2021-03-25 14:43:10 -04:00
Noah Boorstin
44060b579b busybear: quick fix to mem reading 
also stop ignoring mcause at the start
 2021-03-25 14:29:11 -04:00
Brett Mathis
162f2df880 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Domenico Ottolia
f134b09a97 Fix bugs with privileged tests 2021-03-25 14:06:05 -04:00
Noah Boorstin
d02c88dab5 busybear: stop NOPing out atomics 
and bump regression to check for 800k instrs, up from 200k
 2021-03-25 13:29:56 -04:00
Jarred Allen
0290568a52 Make cache output NOP after a reset 2021-03-25 13:18:30 -04:00
David Harris
eb9787609e testgen-PIPELINE python startup 2021-03-25 13:12:18 -04:00
Shriya Nadgauda
21989ee615 adding PIPELINE tests 2021-03-25 13:07:25 -04:00
Jarred Allen
ce6f102fc5 Clean up some stuff 2021-03-25 13:04:54 -04:00
Jarred Allen
128278ea27 Working for all of rv64i now, but not compressed instructions 2021-03-25 13:02:26 -04:00
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
Jarred Allen
ba95557c44 More progress on icache controller 2021-03-25 13:01:11 -04:00
Jarred Allen
ad0d77e9e1 Begin rewrite of icache module to use a direct-mapped scheme 2021-03-25 13:01:10 -04:00
Jarred Allen
ebd6b931c6 Fix bug in cache line 2021-03-25 12:59:30 -04:00
Jarred Allen
b774d35c34 Output NOP instead of BAD when reset 2021-03-25 12:42:48 -04:00
Jarred Allen
4b92a595ab Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/uncore/dtim.sv
 2021-03-25 12:10:26 -04:00
Teo Ene
51291949d8 Config file for ppa experiments 2021-03-25 10:23:21 -05:00
David Harris
a8abd47fbc Added PPA README 2021-03-25 11:21:31 -04:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
b5fa410e15 added 1 tick delay on tim reads 2021-03-25 02:15:28 -04:00
Jarred Allen
682050a33b Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-03-25 00:51:12 -04:00
bbracker
67b27cd2f5 instrfault direspecting stalls bugfix 2021-03-25 00:44:35 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
e98dd420bc future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822 Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Teo Ene
a3aa103dc7 Fix typo from last commit 2021-03-24 17:09:58 -05:00
Teo Ene
4427b5ec01 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-24 17:04:48 -05:00
Teo Ene
e43849b82c Updated coremark_bare testbench for IM 2021-03-24 17:04:43 -05:00
Katherine Parry
18cb1f4873 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Teo Ene
385ce9a8f9 Added BPTYPE to coremark_bare config 2021-03-24 16:38:29 -05:00
Ross Thompson
a99c0502e5 Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. 2021-03-24 15:56:55 -05:00
Ross Thompson
11109e5a88 Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed. 2021-03-24 13:03:43 -05:00
Domenico Ottolia
d67e28bf50 re-organize privileged tests to be in rv64p to rv32p folders 2021-03-24 13:51:25 -04:00
Jarred Allen
c1fe16b70b Give some cache mem inputs a better name 2021-03-24 12:31:50 -04:00
Jarred Allen
a51257abca Fix compile errors from const not actually being constant (why does Verilog do this) 2021-03-24 00:58:56 -04:00
Ross Thompson
1c6e37120e Fixed RAS errors. Still some room for improvement with the BTB and RAS. 2021-03-23 23:00:44 -05:00
Jarred Allen
4410944049 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
84ad1353e4 Fixed a bunch of bugs with the RAS. 2021-03-23 21:49:16 -05:00
Katherine Parry
56dc8de009 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Ross Thompson
4fb7a1e0a6 Fixed the valid bit issue. Now the branch predictor is actually predicting instructions. 2021-03-23 20:20:23 -05:00
Ross Thompson
49348d734b fixed issue with BTB's valid bit not updating. There is still a problem is valid not ocurring in the correct clock cycle. 2021-03-23 20:06:45 -05:00
Ross Thompson
95dbc5f1fa fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Jarred Allen
d6ecc3ede0 Begin work on direct-mapped cache 2021-03-23 17:03:02 -04:00
Teo Ene
ef3d2dda48 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Ross Thompson
174557ae89 Simulation definitely shows the branch predictor counters and branch predictor don't work. :( 2021-03-23 14:04:58 -05:00
Ross Thompson
5edc90b1c2 added a whole bunch of interseting test code for branches which does not work. 2021-03-23 13:54:59 -05:00
Ross Thompson
6a050219d4 updated the branch predictor config. 2021-03-23 13:54:59 -05:00
Ross Thompson
9e61481414 Added first benchmark. 2021-03-23 13:54:59 -05:00
Ross Thompson
2b0f7cdd42 Temporary exe2memfile0.pl script to support starting addresses of 0. 2021-03-23 13:54:59 -05:00
Ross Thompson
e1842c8da6 Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses. 2021-03-23 13:54:59 -05:00
Noah Boorstin
69e5319675 busybear: more progress 2021-03-23 14:49:30 -04:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
0d05c51af9 Remove deleted signal from waves 2021-03-23 14:17:17 -04:00
Noah Boorstin
24e403bc35 busybear: more progress moving from instrf to instrrawd 2021-03-23 14:06:21 -04:00
Noah Boorstin
f3194c6388 busybear: ignore illegal instruction when starting 2021-03-23 13:28:56 -04:00
Jarred Allen
7da8af4c68 Another tweak to regression-wally.py comments 2021-03-23 00:18:38 -04:00
Jarred Allen
0f8fe8fb3b Document some internal signals 2021-03-23 00:10:35 -04:00
Jarred Allen
6ffa01cc4d Add comments explaining icache inputs 2021-03-23 00:07:39 -04:00
Jarred Allen
82de84469f Slight change to regression-wally.py comments 2021-03-23 00:02:40 -04:00
Jarred Allen
827993598d Small commit to see if new hook tests non-main branch 2021-03-22 23:57:01 -04:00
Noah Boorstin
d5bd5fa9d7 start migrating busybear over to InstrRawD/PCD 
this breaks busybear for now
 2021-03-22 23:45:04 -04:00
Noah Boorstin
15474f678d Merge branch 'main' into cache 2021-03-22 23:28:30 -04:00
Noah Boorstin
849641f31e busybear: add better warning on illegal instruction 
...also it seems that mret is being picked up as an illegal instruction??
 2021-03-22 18:24:35 -04:00
Noah Boorstin
34b8f750ce busybear: temporarially force rf[5] correct after failure to read CSR 2021-03-22 18:12:41 -04:00
Noah Boorstin
77dd0b4504 busybear: allow overwriting read values 2021-03-22 17:28:44 -04:00
Noah Boorstin
7bb31c3287 busybear: finally get the right error 2021-03-22 16:52:22 -04:00
bbracker
5efd5958e7 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
Jarred Allen
6ce52f9b80 Remove DelaySideD since it isn't needed 2021-03-22 15:13:23 -04:00
Jarred Allen
b871bfe714 Update icache interface 2021-03-22 15:04:46 -04:00
Noah Boorstin
2aa76b27e1 busybear: comment out some debug printing 2021-03-22 14:54:05 -04:00
Jarred Allen
3f897bbf53 Merge branch 'main' into cache 2021-03-22 14:50:22 -04:00
Noah Boorstin
74bcd9b994 regression: expect 200k instead of 100k busybear instrs 
and a minor busybear bugfix
 2021-03-22 14:47:52 -04:00
Jarred Allen
3748d03adc Merge branch 'main' into cache 2021-03-22 13:47:48 -04:00
bbracker
11d4a8ab34 first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
f741ba7702 fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Jarred Allen
5b1db9b6a2 Change busybear testbench to reflect new location of InstrF 2021-03-20 18:20:27 -04:00
Jarred Allen
097e8edb3d Put Imperas testbench back 2021-03-20 18:19:51 -04:00
Jarred Allen
f9cf05a7d4 Fix bug with PC incrementing 2021-03-20 18:06:03 -04:00
Jarred Allen
a3a646d1a9 Merge branch 'main' into cache 2021-03-20 17:56:25 -04:00
Jarred Allen
a2bf5ac202 Fix another bug in the icache (why so many of them?) 2021-03-20 17:54:40 -04:00
Jarred Allen
c5f99c4a34 Revert "Change flop to listen to StallF" 
This reverts commit c8028710a5.
 2021-03-20 17:34:19 -04:00
Jarred Allen
b63bfc7afa Fix conflicts in ahb-waves that snuck through manual merging 2021-03-20 17:16:50 -04:00
Jarred Allen
c8028710a5 Change flop to listen to StallF 2021-03-20 17:04:13 -04:00
Katherine Parry
e317e7511e messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
Jarred Allen
279c09b27c Merge changes from main 2021-03-18 18:58:10 -04:00
Jarred Allen
2a29def21c Add icache's read request to ahb wavs 2021-03-18 18:52:03 -04:00
bbracker
85363e941d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
bbracker
98e93a63c0 maybe AHB works now 2021-03-18 17:47:00 -04:00
Shreya Sanghai
09faa40eb6 fixed minor bugs in testbench 2021-03-18 17:37:10 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
8d484174a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Thomas Fleming
7d4906b1c7 Improve page table creation in python file 2021-03-18 14:27:09 -04:00
Noah Boorstin
bc1a0c6ee7 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e everyone gets a bootram 2021-03-18 12:35:37 -04:00
Noah Boorstin
ced2a32d21 busybear: update memory map, add GPIO 2021-03-18 12:17:35 -04:00
Teo Ene
57f1ca5259 Switched coremark to RV64IM 2021-03-17 22:39:56 -05:00
Teo Ene
d2fe42d6d0 adapted coremark bare testbench to new dtim RAM HDL 2021-03-17 16:59:02 -05:00
Jarred Allen
e69376c823 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
4fd0ecff69 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Teo Ene
7446a7b479 fix to last commit 2021-03-17 15:07:02 -05:00
Teo Ene
3e849f99a6 fix to last commit 2021-03-17 15:02:15 -05:00
Teo Ene
d72d774a0b addition to last commit 2021-03-17 14:52:31 -05:00
Teo Ene
dfe6df2e00 Added Ross's addr lab stuff to coremark stuff 2021-03-17 14:50:54 -05:00
Elizabeth Hedenberg
041439c008 fixing coremark branch prediction 2021-03-17 15:15:55 -04:00
Elizabeth Hedenberg
d0ddb5f461 replicating coremark changes into coremark bare 2021-03-17 14:36:34 -04:00
Elizabeth Hedenberg
da758e9e14 Merge branch '3_3_2021' into main 
Making sure coremark works with spring break changes
 2021-03-17 14:11:37 -04:00
Ross Thompson
f070aae847 Fixed issue with sim-wally-batch. Are people still using this script? 2021-03-17 11:17:52 -05:00
Ross Thompson
3618a39087 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-17 11:07:57 -05:00
Ross Thompson
9f8f0242ca Added possibly working OSU test bench as a precursor to running a bp benchmark. 
Fixed a few bugs with the function radix.
 2021-03-17 11:06:32 -05:00
Domenico Ottolia
487b198055 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-16 23:27:09 -04:00
Domenico Ottolia
748372dc45 Add test runner for privileged 2021-03-16 23:26:59 -04:00
Noah Boorstin
bfa7aedd35 busybear: add seperate message on bad memory access becasue its confusing 2021-03-16 21:42:26 -04:00
Noah Boorstin
e7fae21eb8 busybear: add COUNTERS define 2021-03-16 21:08:47 -04:00
Domenico Ottolia
d354cbd37d Add privileged testbench 2021-03-16 20:28:38 -04:00
Domenico Ottolia
82ea97e304 Add privileged tests for mcause 2021-03-16 19:22:36 -04:00
Domenico Ottolia
1ceb7a7431 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-16 19:12:21 -04:00
Jarred Allen
152ffd16e2 Undo accidental change 2021-03-16 18:16:00 -04:00
Jarred Allen
ae5417195a Condense the parallel and non-parallel wally-pipelined-batch.do files into one 2021-03-16 18:15:13 -04:00
Jarred Allen
f6cbe44cbd Change busybear to only check that first 100k instructions load 2021-03-16 17:43:39 -04:00
Shreya Sanghai
36f0631203 added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Jarred Allen
a82aa23399 Fix icache for jumping into misaligned instructions 2021-03-16 16:57:51 -04:00
Domenico Ottolia
b2faf3c888 Add privileged tests folder 2021-03-16 16:11:20 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Jarred Allen
2d2092e8ab Merge remote-tracking branch 'origin/main' into cache 2021-03-16 14:17:39 -04:00
Shreya Sanghai
08e9149e20 made performance counters count branch misprediction 2021-03-16 11:24:17 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
Jarred Allen
36452749d7 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Noah Boorstin
9e1612c166 remove regression-wally.sh 2021-03-15 19:03:57 -04:00
Noah Boorstin
400791163e copy Ross's branch predictor preload change into busybear 2021-03-15 18:27:27 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Ross Thompson
f2a6e8c6cf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
The last commit message about rv32ic having issues is now invalid. Looks like the issue was resolved.
 2021-03-15 12:06:18 -05:00
Ross Thompson
806cfc4ea5 Fixed the parallel script so the rv64ic passes. 
rv32ic and busybear still have issues.
 2021-03-15 12:04:59 -05:00
Jarred Allen
ac9fd5a323 Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
deb13f34bb Get non-jump case working 2021-03-14 14:46:21 -04:00
bbracker
e58d17d5b7 slightly smarter dtim HREADY 2021-03-13 07:03:33 -05:00
bbracker
345254b5a3 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
c5015e5809 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
Ross Thompson
940d892f29 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 20:18:35 -06:00
Ross Thompson
7ceef2b0c6 Fixed the issue with the batch mode not working after adding the function radix. 2021-03-12 20:16:03 -06:00
bbracker
f4fb546969 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
86078d856f Cleaned up the function radix exractFunctionRadix script. I should change the name as this is no longer a modelsim radix. 2021-03-12 15:29:02 -06:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3 Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
56b690ccb9 Drafted rv32a tests 2021-03-12 00:06:23 -05:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Ross Thompson
318b642359 Improve version of the function radix which does not cause the wave file rendering to slow down. 2021-03-11 17:12:21 -06:00
Noah Boorstin
cc94046084 test regression script: add commented out rv32ic tests 2021-03-11 12:57:54 -05:00
Noah Boorstin
394b79b5de add rv32ic regression test 2021-03-11 12:40:29 -05:00
Noah Boorstin
54fa16d783 test regression script: parallalize better 2021-03-11 12:25:20 -05:00
Noah Boorstin
aba54659bf test regression script: try adding verilator checking also 2021-03-11 07:32:31 +00:00
Noah Boorstin
81c14f899d try adding delays to test regression script 2021-03-11 06:59:50 +00:00
Noah Boorstin
1093b07670 this is just a test for now, try to reimplement regression-wally in bash 2021-03-11 06:45:45 +00:00
Noah Boorstin
a8b242a6ef busybear: account for CSR moving 2021-03-11 06:45:14 +00:00
Thomas Fleming
1294235837 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
42275e92ed Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Jarred Allen
4757794887 Return testbench to normal 2021-03-10 22:58:41 -05:00
Ross Thompson
845115302e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
f92f766573 Added debug option to disable the function radix if not needed. 
Function radix slows the simulation by 70 to 76 s (8.5%) for the rv64i tests.
 2021-03-10 15:17:02 -06:00
Ross Thompson
dcae90e3ad I finally think I got the function radix debugger working across both 32 and 64 bit applications. 2021-03-10 14:43:44 -06:00
Noah Boorstin
2c25e270a2 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
Ross Thompson
50a92247b3 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
ae9bcc174d Merge upstream changes 2021-03-09 21:20:34 -05:00
Jarred Allen
3172be3039 More progress 2021-03-09 21:16:07 -05:00
David Harris
c2f340681d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-09 09:28:32 -05:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Noah Boorstin
4a8b689f62 busybear: better NOPing out of float instructions 2021-03-08 21:24:19 +00:00
Noah Boorstin
c780a25f92 busybear: better instrF checking 
So this now checks instrF only when StallD is low. @kaveh I'd love your
opinion on this. I don't know if this is a good idea or not. Ideally we
should probably be checking InstrRawD instead, but I kind of want to stay
checking the instr in the F stage instead of D for now. Idk if this is worth
staying in F, I can't really see any big downsides to checking the instruction in
D except that PCD isn't an external signal, but neither is StallD, so.....
Anyway I'd love others' thoughts on this
 2021-03-08 19:48:12 +00:00
Noah Boorstin
1b206d5a3c busybear: make a second .do file with better optimization for command line mode 2021-03-08 19:35:00 +00:00
Noah Boorstin
93c9c57426 busybear: load mem files from verilog instead of .do 2021-03-08 19:26:26 +00:00