Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-02 17:55:19 +00:00
Code Issues Packages Projects Releases Wiki Activity
10,532 Commits 4 Branches 2 Tags 53 MiB
fb1ffa86ce
Commit Graph

1641 Commits

Author SHA1 Message Date
Rose Thompson
d706b5b898 Fixed bus width error. Have to check this FPGA to make sure this didn't break anything. 2024-07-23 12:26:03 -05:00
Rose Thompson
bb74a0f96b Resolved more lint errors in the rvvi synthesized hardware. 2024-07-23 12:23:04 -05:00
Rose Thompson
b30656447f Resolved more lint errors in the rvvi synthesized hardware. 2024-07-23 12:23:04 -05:00
Rose Thompson
94a1ce32e7 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-22 17:48:34 -05:00
Rose Thompson
c6c2240630 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-07-22 17:48:34 -05:00
Rose Thompson
121342f4cc Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Rose Thompson
3c06556833 Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI. 2024-07-22 16:12:06 -05:00
Jacob Pease
c50df29e58 Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-07-22 13:06:05 -05:00
Jacob Pease
6a9141e3be Merge branch 'main' of github.com:openhwgroup/cvw into spiboot 2024-07-22 13:06:05 -05:00
Jacob Pease
a722c3c0a1 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Jacob Pease
a506d76149 Removed the old SDC. Added a second SPI peripheral that now will be used to control the SD card. SPI peripheral now outputs SPICLK. Removed references to the now non-existent external SDC in uncore. Removed all of the AXI Xilinx IP. 2024-07-22 12:36:39 -05:00
Rose Thompson
00c30239bf Cleaned up rvvisynth.sv 2024-07-22 12:22:41 -05:00
Rose Thompson
35e69944fa Cleaned up rvvisynth.sv 2024-07-22 12:22:41 -05:00
Rose Thompson
7223b15134 Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
Rose Thompson
02f108345a Merge branch 'rvvi' 2024-07-22 12:01:01 -05:00
David Harris
c4400dfeb0 Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode 2024-07-22 08:45:08 -07:00
David Harris
13f1aa1ebf Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode 2024-07-22 08:45:08 -07:00
Rose Thompson
9471dcd296 Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. 
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
 2024-07-19 17:08:47 -05:00
Rose Thompson
0d40b8c933 Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00
Rose Thompson
a324e79b6f Updated the ethernet frame gap for a faster computer. 2024-07-19 13:12:13 -05:00
David Harris
c64c12dc6c Detect illegal compressed immediates, hints 2024-07-18 22:48:32 -07:00
David Harris
12c8449275 Detect illegal compressed immediates, hints 2024-07-18 22:48:32 -07:00
David Harris
945722cd5b Neatly formatted decompress.sv 2024-07-18 22:01:43 -07:00
David Harris
bd1658754f Neatly formatted decompress.sv 2024-07-18 22:01:43 -07:00
David Harris
ebea314a6e Modified decompressor to look for illegal x0 values and hints 2024-07-18 21:38:17 -07:00
David Harris
a4e84d6f15 Modified decompressor to look for illegal x0 values and hints 2024-07-18 21:38:17 -07:00
David Harris
3b4726ea99 Check legal compressed nonzero destination registers, add c.nop decoding 2024-07-18 09:30:16 -07:00
David Harris
1637f4f1e3 Check legal compressed nonzero destination registers, add c.nop decoding 2024-07-18 09:30:16 -07:00
David Harris
df063acf61 Refactored decompression to use simpler default illegal instruction 2024-07-18 08:26:58 -07:00
David Harris
566583639d Refactored decompression to use simpler default illegal instruction 2024-07-18 08:26:58 -07:00
David Harris
25f271064f Fixed slli.uw bug reported by Lee Moore 16 July 2024 2024-07-16 09:28:05 -07:00
David Harris
8f83ff1a94 Fixed slli.uw bug reported by Lee Moore 16 July 2024 2024-07-16 09:28:05 -07:00
Ross Thompson
f0096f5a43 Yay. It's actually working! The FPGA/ImperasDV hybrid is working. 2024-07-10 15:10:37 -05:00
Ross Thompson
e6dc962d11 Yay! the trigger is correctly working now! 2024-07-10 12:05:10 -05:00
Ross Thompson
cf986b5fb8 Really close to having the trigger in module work. 
Can trigger on the data of the correct frame, but trigger in is still not
working.
 2024-07-09 19:04:51 -05:00
David Harris
84c687080d Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-07-05 21:42:26 -07:00
David Harris
9f5e7b8653
Merge pull request #851 from kevindkim723/intdivb 
Reduce Bit widths for IDIV on FPU
 2024-07-05 21:42:19 -07:00
David Harris
ffb248dc65 Fixed issue 868 about tlbmisc.S coverage test failing due to HPTW writing wrong address when updateing A bit 2024-07-05 21:32:57 -07:00
David Harris
af4403342f renamed run_vcs.py to run_vcs, added instr/data in ebu 2024-07-03 08:02:38 -07:00
Kevin Kim
b04d387e7c removed redundant signals 2024-06-28 22:13:35 -07:00
Kevin Kim
6cb6ff429b Revert "intdivble changes" 
This reverts commit 3618c6c593.
 2024-06-28 21:28:09 -07:00
Kevin Kim
3618c6c593 intdivble changes 2024-06-28 21:19:10 -07:00
Jordan Carlin
032de34dbd
Lint fixes for no priv mode configs 2024-06-26 22:15:18 -07:00
Jordan Carlin
c3cb4e5d1c
Fix FPU without S_SUPPORTED - #840 2024-06-26 22:00:29 -07:00
Ross Thompson
612a281f62 Added module to receive ethernet frame and trigger the ila. 2024-06-26 11:05:31 -07:00
Kevin Kim
eeea783da0 lint 2024-06-21 23:15:34 -07:00
Kevin Kim
e6dc50308a integer postprocessing hardware matches diagram 2024-06-21 21:50:55 -07:00
Kevin Kim
00bf3faa9c changed intdivb width 2024-06-21 21:31:19 -07:00
Kevin Kim
9a59c8e07f reduced bit widths for integer on fpu 2024-06-20 23:46:45 -07:00
Ross Thompson
249d58244a It's working!!!!!! 2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3 Added some debug code to count frames sent to the ethernet mac and frames sent to the phy. 
Removed the external reset of the phy and now it always reliably starts in the same way.  The first 0x117 frames are always captured.
 2024-06-20 12:54:12 -07:00
David Harris
0ab3f28991 Lint cleanup 2024-06-20 00:10:03 -07:00
David Harris
5f1ee1ac85 Fixed undriven signal in certain config 2024-06-19 15:12:35 -07:00
David Harris
9922b24cbe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-06-19 14:13:08 -07:00
Ross Thompson
685f4d3807 Removed the last of the ***. 2024-06-19 14:00:31 -07:00
Ross Thompson
7f0ba87231 Updated comments in uart. 2024-06-19 13:51:30 -07:00
Ross Thompson
91c844ca45 Removed more *** from camline and csrc. 2024-06-19 12:31:50 -07:00
Ross Thompson
576f1b9e59 Moved the *** from trap to an issue. 2024-06-19 12:31:24 -07:00
Ross Thompson
9b6b6617af Cleaned up hptw. 2024-06-19 12:02:56 -07:00
Ross Thompson
24916d42e2 Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw. 2024-06-19 11:40:02 -07:00
Ross Thompson
71f267a17a Added InstrUpdateDAF to the HPTW. 2024-06-19 11:09:49 -07:00
Ross Thompson
77523c52c2 LSU no longer has ***. 2024-06-19 10:56:07 -07:00
Ross Thompson
5e5ca0809f Removed more *** from lsu and updated assertions for dtim. 2024-06-19 10:52:51 -07:00
Ross Thompson
4911642427 Removed *** and updated comments for bpred and align. 2024-06-19 10:31:44 -07:00
Ross Thompson
f0e5bbef0c Removed remaining *** from IFU. 2024-06-19 09:52:40 -07:00
Ross Thompson
cc58bfdcf3 Removed more *** from the ifu. 2024-06-19 09:49:17 -07:00
Ross Thompson
ab1ee3d69b Removed *** from IFU, lrcs. 2024-06-19 09:40:35 -07:00
Ross Thompson
ab1af0fabf Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2024-06-19 09:25:39 -07:00
David Harris
10e6d5846b Removed unnecessary Umfirst from early termination 2024-06-19 09:18:51 -07:00
David Harris
4b4980e42d Fixed undriven OutFmt 2024-06-19 09:17:32 -07:00
David Harris
54cb612577 Fixed lint error in fdivsqrtpreproc for rv32 IDIV_ON_FPU 2024-06-19 07:48:54 -07:00
Ross Thompson
2581ea0b74 Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames. 2024-06-18 16:48:49 -07:00
David Harris
301ded05f8 Unused signal cleanup 2024-06-18 08:15:48 -07:00
David Harris
cb563e8018 Clean up unused signals 2024-06-18 08:07:14 -07:00
Ross Thompson
00e0549c36 I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word. 
The default input interface to the interface is 8-bit and I used 32-bit.  I suspect there is a bug in the implementation for non-8-bit interfaces.
 2024-06-18 07:44:19 -07:00
David Harris
c1fd7a9589 Removed unused signals 2024-06-18 07:28:52 -07:00
David Harris
8bae52b09d Lint cleanup of unused signals 2024-06-18 06:49:17 -07:00
David Harris
45f505250c Lint cleanup 2024-06-18 06:23:43 -07:00
David Harris
3fa37b0233 Lint cleanup 2024-06-18 06:15:17 -07:00
David Harris
cac67aae4f Lint cleanup 2024-06-18 05:58:54 -07:00
David Harris
ecae1100f6 Lint cleanup 2024-06-18 05:49:49 -07:00
David Harris
7509e856df Removed asynchronous reset causing lint issue in peripherals 2024-06-18 05:49:12 -07:00
David Harris
2fc9edff45 Fixed Issue #752 of Verilator simulation by changing LRUMemory to be nonblocking now that Verilator handles this construct properly 2024-06-18 04:40:38 -07:00
Ross Thompson
cccb40e4b5 Got the tracer not overrunning ethernet buffers so frames are not being dropped. 2024-06-17 09:16:24 -07:00
David Harris
4a4bbdfc43 More code cleanup 2024-06-14 09:50:07 -07:00
David Harris
53477b2c85 Code cleanup 2024-06-14 07:08:17 -07:00
David Harris
8f09240e6c Simplified outdated documentation pointers 2024-06-14 03:42:15 -07:00
David Harris
b1c9450b4a Code cleanup: RAM, fdivsqrt 2024-06-14 03:35:05 -07:00
David Harris
6789f32154 Starting code cleanup 2024-06-14 02:54:43 -07:00
Ross Thompson
47523c97ac Getting closer to figuring out the lost ethernet frame bugs. 2024-06-13 15:46:54 -07:00
Rose Thompson
b77fcd70e6 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-06-13 13:58:07 -05:00
David Harris
28142eff64 Formatting shiftcorrection 2024-06-12 04:25:13 -07:00
David Harris
b7e2f34966 shiftcorrection cleanup 2024-06-12 03:59:55 -07:00
Ross Thompson
563980443a Merge branch 'main' into rvvi 2024-06-10 18:10:23 -07:00
David Harris
e02c1008bc postprocessor shift amount simplification 2024-06-10 07:55:35 -07:00
David Harris
3284dd2112 Removed unnecessary Zero checking on FmaPreResultSubnorm 2024-06-10 07:45:03 -07:00
David Harris
4c066c078f Removing two unnecessary 0's from fmashiftcalc interface 2024-06-10 07:38:03 -07:00
David Harris
1873064be5 Simplified fround exact case 2024-06-10 06:23:42 -07:00
David Harris
5094122048 Simplifying fround 2024-06-10 06:11:55 -07:00
David Harris
8b887755c9 Simplified 3:1 mux to 2:1 mux when only Zbkc is supported and clmulr is not needed 2024-06-10 02:34:35 -07:00
Rose Thompson
5dfde808f0
Merge pull request #827 from davidharrishmc/dev 
Fixed support for individual crypto extensions without Zb*
 2024-06-06 09:31:07 -05:00
David Harris
9489771bd7 Fixed support for individual crypto extensions without Zb* 2024-06-05 22:57:39 -07:00
Rose Thompson
fc62f80407 Closer to fully working hardware tracer. 2024-06-04 11:31:05 -05:00
Rose Thompson
80f98b3223 now have a working ethernet daemon to collect frames and partially decode into RVVI. 2024-06-04 10:20:51 -05:00
Rose Thompson
dc904cdbbb The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field. 2024-06-03 18:10:25 -05:00
Rose Thompson
0ca10e7ee2 Last of the branch predictor signal name updates. 2024-06-02 17:01:51 -05:00
Rose Thompson
04744032d8 Updated more signal names to match book. 2024-06-02 16:59:11 -05:00
Rose Thompson
b45b7ff7d6 Signal name changes to match book. 2024-06-02 16:32:25 -05:00
Rose Thompson
731e1fe08f Updated spill logic to reflect changes in textbook. 2024-06-02 15:48:42 -05:00
Rose Thompson
a830bd57f0 Have to reverse the byte order for ethernet frame length. 2024-05-31 17:46:43 -05:00
Rose Thompson
e05ebc30b8 Almost worked out the bugs in packetizer. 2024-05-31 16:48:41 -05:00
Rose Thompson
0dccc6051d draft of receiving code to unpack the ethernet frames into rvvi. 2024-05-31 13:55:25 -05:00
Rose Thompson
1df3e5239a This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer. 
wireshark is able to capture the frames and they match the expected data!
 2024-05-30 17:57:28 -05:00
Rose Thompson
ca90c6ba48 Added the ethernet files. These are part of another repo. 
We should remove before mainlining this.
 2024-05-30 16:33:49 -05:00
Rose Thompson
9703055758 The FPGA is synthesizing with the rvvi and ethernet hardware. 2024-05-30 15:37:17 -05:00
Rose Thompson
84946919a4 Changed name CacheWriteData to WriteData. 2024-05-28 18:00:39 -05:00
Rose Thompson
273b41df99 Changed name of cache parameter NUMLINES to NUMSETS to better match book. 2024-05-28 17:55:43 -05:00
Jordan Carlin
6f7a802b86
Merge branch 'main' of https://github.com/openhwgroup/cvw into fround_fixes 2024-05-26 14:40:26 -07:00
Jordan Carlin
b830d20f2d
Modify Fround Tmask to work for X=1 2024-05-25 12:56:02 -07:00
Jordan Carlin
fb77440a64
Update fpctrl fmt to work for fround instructions 2024-05-24 15:33:45 -07:00
Jordan Carlin
ae29a9b861
Update control bits for froundnx 2024-05-24 15:19:20 -07:00
Rose Thompson
dc09e1c0c5 Modified names so they don't conflict with FPGA's axi signals. 2024-05-24 16:38:47 -05:00
Rose Thompson
73261e7f89 More cleanup. Close to the simpliest it can be. 2024-05-24 16:34:33 -05:00
Rose Thompson
bd2ec879d2 Removed unused axi signals from packetizer. 2024-05-24 16:31:27 -05:00
David Harris
a95977590d AES cleanup 2024-05-24 14:28:30 -07:00
Rose Thompson
263be86119 Packetizer cleanup. 2024-05-24 16:27:09 -05:00
David Harris
b2689b4f01 AES cleanup 2024-05-24 14:13:57 -07:00
Rose Thompson
1f7d732dca Moved the rvvisynth code to testbench since I only want this for simulation and fpga. 2024-05-24 16:10:58 -05:00
Rose Thompson
d341974c5b Have rvvi to ethernet working. 
Now it is time to move the hardware to the FPGA.
Ideally I don't want Wally to actually have any of this code since it's entirely
debug code so it will move to the fpga/src directory.
Then we'll need to add additional logic to the mmcm to generate the correct clocks.
Finally we'll update the I/O to add ethernet.
 2024-05-24 15:52:13 -05:00
David Harris
ec5c67a5c1 AES cleanup 2024-05-24 13:48:53 -07:00
Rose Thompson
bf9f45d319 We have a simulation of the ethernet transmission working. 
This commit does not include the source files for the ethernet as it does not belong to cvw.
I'll want to fork that repo and make it a submodule as I need to change the source a bit.
 2024-05-24 11:25:42 -05:00
David Harris
e626052ec9 simplified AES32de mixcolumns because input is only one byte 2024-05-23 22:30:25 -07:00
David Harris
b0d1344121 Commented sha instructions 2024-05-23 22:06:37 -07:00
David Harris
ac153bc4ed More simplifying sha512_32 2024-05-23 05:46:56 -07:00
David Harris
d9a1691c83 Simplified sha512_32 2024-05-23 05:39:50 -07:00
David Harris
c160ced2d2 Zk* cleanup 2024-05-22 15:01:20 -07:00
David Harris
3ad815ce34 Reordered Zicond support in ALU 2024-05-22 08:29:08 -07:00
Rose Thompson
e5b8fd35b0 Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up. 2024-05-22 09:56:12 -05:00
David Harris
a17204b0fe Continued bmu cleanup 2024-05-22 00:48:04 -07:00
David Harris
88eb7bd045 Pulled brev8 out of byteop so redundant byteop logic is not needed in zbkb 2024-05-22 00:22:53 -07:00
Rose Thompson
b116c0c902 Lots of progress on the rvvisynth to ethernet packetizer. 
Almost producing axi4 commands.
 2024-05-21 18:23:42 -05:00
Rose Thompson
d1141237ee Removed prefix from rvvi hierarchy so it works without testbench. 2024-05-21 16:20:53 -05:00
Rose Thompson
8fd278b322 Fixed some references to rvvi. 2024-05-21 16:15:05 -05:00
Rose Thompson
ea5d780adf Closer to synthesized rvvi 2024-05-21 12:42:43 -05:00
Rose Thompson
b127c19242 Merge branch 'main' into rvvi 2024-05-20 16:31:06 -05:00
Jordan Carlin
1d8ffee20c
Certain Zcb instructions are dependent on other extensions, not the entire extension 2024-05-15 19:16:43 -07:00
Jordan Carlin
3df5a5abdd
Remove additional bitwise operator 2024-05-15 09:29:54 -07:00
Rose Thompson
e295454948
Merge pull request #798 from jordancarlin/newConfig 
Update config to derive MISA from macros and update MISA bits based on the spec
 2024-05-15 10:28:44 -05:00
Jordan Carlin
291d1e62d5
M implies Zmmul 2024-05-14 19:38:34 -07:00
Jordan Carlin
4a72922087
update config to derive MISA from macros 
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
 2024-05-14 06:49:18 -07:00
David Harris
175c18da01 Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes 2024-05-13 15:16:00 -07:00
David Harris
2dfada0687 Started parameterizing FMA 2024-05-13 14:01:36 -07:00
David Harris
c2b9e326ca Fround cleanup 2024-05-13 13:27:29 -07:00
David Harris
e87a269f59 Fix fcvt.lu.s bug and lint issue in packoutput 2024-05-12 11:31:27 -07:00
David Harris
380d88fc68 Merged config-shared after fma fix 2024-05-12 11:10:55 -07:00
David Harris
009d251433 Fixed cvtint bug by adding 2 bits to convert width; initial implementation of fround passes basic regression but fails some nightly regression cases 2024-05-11 22:32:51 -07:00
Katherine Parry
807ef44772 fixed fma testfloat issue #578 2024-05-10 18:12:11 -07:00
Rose Thompson
b027fa44ef Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-05-10 08:53:00 -05:00
Rose Thompson
10b08f8039 Updated brach predictor names to more logical names and match textbook. 2024-05-10 08:51:12 -05:00
David Harris
77137f0f60 ZAAMO and ZALRSC implemented but not tested 2024-05-07 16:45:49 -07:00
David Harris
fcd75fd6b6 Fixed shiftcorrection typo causing failure on testfloat fcvt tests 2024-05-07 14:27:44 -07:00
David Harris
bdc2ad494f Shared AND gate in ALU for extract / and paths 2024-05-03 09:07:33 -07:00
David Harris
4d5ac3b869 Turned off BMUSubArith for bext/bexti 2024-05-03 08:59:40 -07:00
David Harris
4639e92fda Turned off BMUSubArith for bext/bexti 2024-05-03 08:56:14 -07:00
David Harris
c0afb44ed4 Tied dangling signals to 0 for some configs to make VCS lint happy 2024-04-28 22:50:36 -07:00
David Harris
7695ad4755 More fround stub code to keep VCS happy 2024-04-28 22:21:51 -07:00
David Harris
06e34b7be4 Fixed byte enables for synthesis 2024-04-27 06:25:24 -07:00
David Harris
1274ec55af Resolved merge conflict 2024-04-26 16:15:23 -07:00
David Harris
4faf44c4c6 Named zknde block in bitmanipalu 2024-04-25 17:24:00 -07:00
Rose Thompson
6c0b860742 Fixed the cache miss counter. 2024-04-24 16:14:51 -05:00
David Harris
235a3dcfca ROM preload compatible with Verilator lint, sim, and Design Compiler 2024-04-24 08:44:37 -07:00
David Harris
32b6e6a8ab fround progress 2024-04-24 04:42:47 -07:00
David Harris
6415bfc3c2 Code and testbench cleanup 2024-04-23 10:17:44 -07:00
David Harris
cc236bdb25 Resolved merge conflicts 2024-04-22 12:16:06 -07:00
David Harris
03f49dea3f regression printing improvements 2024-04-21 19:45:09 -07:00
David Harris
3f195884e9 Defined bit sizes more precisely to help VCS lint and conform to coding style 2024-04-21 08:40:11 -07:00
David Harris
be15a11622 Fixed conflicts on getenv 2024-04-21 08:38:13 -07:00
David Harris
0419b5484a parameterized register names in peripherals 2024-04-21 07:43:01 -07:00
David Harris
00a1c0fc57 Fixed WALLY/RISCV paths in testbench/rom1p1r; search log files for warnings and errors 2024-04-21 00:02:15 -07:00
David Harris
fd6a6b2249 environment variable cleanup 2024-04-20 22:52:08 -07:00
David Harris
f39e240082 Spacing cleanup 2024-04-20 20:53:49 -07:00
David Harris
25a26656b6 Removed unnecessary ZBB from BMU extract mux 2024-04-20 20:53:14 -07:00
David Harris
338f37b570 Moved getenv/getenvval declaration to config-shared so lint and regression both run 2024-04-20 17:19:42 -07:00
David Harris
571b67f565 Merging PR738 2024-04-20 17:15:17 -07:00
slmnemo
f0229e970b Fixed getenvvar verilator bug in rom1p1r, Removed unused system function from testbench. 2024-04-20 17:07:54 -07:00
David Harris
ea344fe2fa Fixed getenvval lint error in rom1p1r 2024-04-20 15:55:52 -07:00
David Harris
a3db61b2b2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-04-20 15:41:42 -07:00
David Harris
9ec4c752f1 Fixed bugs in Zcb compressed loads and stores 2024-04-20 13:16:31 -07:00
Kunlin Han
08dd2eac74 Add getenvval for rom. Related to issue #723. 2024-04-17 23:26:09 -07:00
David Harris
3ea16c6057 Removed note about store stall being depricated 2024-04-17 03:34:11 -07:00
David Harris
db330b35b2 Removed unnecessary muxes from shiftcorrection; changed flag to --nightly in lint-wally 2024-04-16 20:57:49 -07:00
slmnemo
39ae26a897 Added documentation for known Verilator hierarchy bug 2024-04-15 15:58:09 -07:00
slmnemo
4b80457f3e Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory 2024-04-12 21:58:20 -07:00
David Harris
499e4d6a6e Changed 2 to 1 in FmaPreResultSubnorm logic, fixing issue 655 about multiply on f/fh. Not entirely confident this is the right change, but can't find any failures. See https://docs.google.com/document/d/1p7zb4Vvd1LMBLRgEpXjHyp7etCaFaiBVrBZJM8jediE/edit 2024-04-03 17:28:31 -07:00
David Harris
79cccfca82 Progress toward run_vcs 2024-04-03 14:05:07 -07:00
Rose Thompson
4eb522123f Changed D suffix to Delay in ebufsmarb. 2024-03-28 16:24:45 -05:00
Rose Thompson
5b4d3f49b0 Fixed #689 caused by removal of #1 delays. For some reason the #1 were not removed from cacheLRU.sv. 2024-03-26 12:26:03 -05:00
David Harris
fc158689ad Shared amoalu max/min comparator hardware and removed input sign extend muxes 2024-03-24 17:15:46 -07:00
David Harris
f0b29d3083 AMO max/min comparator optimization 2024-03-24 17:05:32 -07:00
David Harris
bae52cf13d
Merge pull request #678 from Karl-Han/latest 
[Resolved Conflict] Remove all #delay from non-testbench
 2024-03-23 15:18:04 -07:00