Simplified outdated documentation pointers

src/cache/cache.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Implements the I$ and D$. Interfaces with requests from IEU and HPTW and ahbcacheinterface
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.9, 7.10, and 7.19)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/cache/cacheLRU.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Implements Pseudo LRU. Tested for Powers of 2.
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figures 7.8 and 7.15 to 7.18)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/cache/cachefsm.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Controller for the cache fsm
 //
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/cache/cacheway.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.11)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/cache/subcachelineread.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Muxes the cache line down to the word size.  Also include possible save/restore registers/muxes.
 //
-// Documentation: RISC-V System on Chip Design Chapter 7
+// Documentation: RISC-V System on Chip Design
 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ebu/ahbcacheinterface.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Translates cache bus requests and uncached ieu memory requests into AHB transactions.
 //
-// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.8)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ebu/ahbinterface.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Translates LSU simple memory requests into AHB transactions (NON_SEQ).
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.21)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ebu/buscachefsm.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Controller for cache to AHB bus interface
 // 
-// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ebu/busfsm.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Simple NON_SEQ (no burst) AHB controller.
 //
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.23)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ebu/controllerinput.sv

@@ -11,7 +11,7 @@
 //          Connects core to peripherals and I/O pins on SOC
 //          Bus width presently matches XLEN
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figure 6.25)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ebu/ebu.sv

@@ -11,7 +11,7 @@
 //          Connects core to peripherals and I/O pins on SOC
 //          Bus width presently matches XLEN
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ebu/ebufsmarb.sv

@@ -8,7 +8,7 @@
 // Purpose: Arbitrates requests from instruction and data streams
 //          LSU has priority.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 6 (Figures 6.25 and 6.26)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fclassify.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point classify unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fcmp.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point comparison unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fctrl.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: floating-point control unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fcvt.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating point conversions of configurable size
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // Int component of the Wally configurable RISC-V project.
 // 

src/fpu/fdivsqrt/fdivsqrt.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Combined Divide and Square Root Floating Point and Integer Unit
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtcycles.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Determine number of cycles for divsqrt
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Exponent caclulation for divide and square root
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 F Addend Generator
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtfgen4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 4 F Addend Generator
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: divsqrt state machine for multi-cycle operations
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: k stages of divsqrt logic, plus registers
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Divide/Square root postprocessing
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Divide/Square root preprocessing: integer absolute value and W64, normalization shift
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: radix-2 divsqrt recurrence stage
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: radix-4 divsqrt recurrence stage
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 unified on-the-fly converter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 4 unified on-the-fly converter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtuslc2.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix 2 Unified Quotient/Square Root Digit Selection
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtuslc4.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Table-based Radix 4 Unified Quotient/Square Root Digit Selection
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fdivsqrt/fdivsqrtuslc4cmp.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Comparator-based Radix 4 Unified Quotient/Square Root Digit Selection 
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fhazard.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Determine forwarding, stalls and flushes for the FPU
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fli.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point float immediate
 // 
-// Documentation: RISC-V System on Chip Design Chapter 16
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fma/fma.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating point multiply-accumulate of configurable size
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.7, 9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fma/fmaadd.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA significand adder
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fma/fmaalign.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA alginment shift
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.10)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fma/fmaexpadd.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA exponent addition
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fma/fmalza.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Leading Zero Anticipator
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.14)
+// Documentation: RISC-V System on Chip Design
 //    See also [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001]
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.

src/fpu/fma/fmamult.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA Significand Multiplier
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.7)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fma/fmasign.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA Sign Logic
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13 (Table 13.8)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fmtparams.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Look up bias of exponent and number of fractional bits for the selected format
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fpu.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating Point Unit Top-Level Interface
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fregfile.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: 3R1W 4-port register file for FPU
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fround.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Floating-point round to integer for Zfa
 // 
-// Documentation: RISC-V System on Chip Design Chapter 16
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/fsgninj.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FPU Sign Injection instructions
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/packoutput.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Pack the output of the FPU
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/cvtshiftcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Conversion shift calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/divshiftcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Division shift calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/flags.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Post-Processing flag calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/fmashiftcalc.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: FMA shift calculation
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/negateintres.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Negate integer result
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/normshift.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: normalization shifter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/postprocess.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Post-Processing: normalization, rounding, sign, flags, special cases
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/resultsign.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: calculating the result's sign
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/round.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Rounder
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/roundsign.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Sign calculation for rounding
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/shiftcorrection.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: shift correction
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/postproc/specialcase.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: special case selection
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/unpack.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: unpack X, Y, Z floating-point inputs
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/fpu/unpackinput.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: unpack input: extract sign, exponent, significand, characteristics
 // 
-// Documentation: RISC-V System on Chip Design Chapter 13
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/generic/decoder.sv

@@ -29,8 +29,5 @@ module decoder #(parameter BINARY_BITS = 3) (
   output logic [(2**BINARY_BITS)-1:0] onehot
 );
 
-  // *** Double check whether this synthesizes as expected
-  //     -- Ben @ May 4: only warning is that "signed to unsigned assignment occurs"; that said, I haven't checked the netlists
   assign onehot = 1 << binary;
-
 endmodule

src/generic/mem/ram1p1rwe.sv

@@ -66,7 +66,7 @@ module ram1p1rwe import cvw::* ; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44) (
     // READ first SRAM model
     //////////////////////////////////////////////////////////////////////////////
   end else begin: ram
-    // *** Vivado is not implementing this as block ram for some reason.
+    // Vivado is not implementing this as block ram for some reason.
     // The version with byte write enables it correctly infers block ram.
 
     bit [WIDTH-1:0]               RAM[DEPTH-1:0];

src/hazard/hazard.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Determine stalls and flushes
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4, Figure 13.54
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/alu.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V Arithmetic/Logic Unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.4)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/bitmanipalu.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension and K extension
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/bitreverse.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Bit reverse submodule
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/bmuctrl.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Top level bit manipulation instruction decoder
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/byteop.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: RISCV bitmanip byte-wise operation unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/clmul.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Carry-Less multiplication unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/cnt.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Count Instruction Submodule
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/ext.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Sign/Zero Extension Submodule
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/popcnt.sv

@@ -5,7 +5,7 @@
 //
 // Purpose: Population Count
 // 
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/zbb.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V ZBB top level unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/bmu/zbc.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V ZBC top-level unit
 //
-// Documentation: RISC-V System on Chip Design Chapter 15
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/comparator.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Branch comparison
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.7)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/controller.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Top level controller module
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/datapath.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Wally Integer Datapath
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/extend.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Produce sign-extended immediates from various formats
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.3)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/ieu.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Integer Execution Unit: datapath and controller
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/regfile.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: 3-port register file
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ieu/shifter.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: RISC-V 32/64 bit shifter
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ifu/bpred/RASPredictor.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: 2 bit saturating counter predictor with parameterized table depth.
 // 
-// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ifu/bpred/btb.sv

@@ -8,7 +8,7 @@
 // Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions.
 //          It also guesses the type of instrution; jalr(r), return, jump (jr), or branch.
 //
-// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ifu/decompress.sv

@@ -6,10 +6,6 @@
 // Modified: 18 January 2023
 //
 // Purpose: Expand 16-bit compressed instructions to 32 bits
-//
-// Documentation: RISC-V System on Chip Design Chapter 11 (Section 11.3.1)
-//                RISC-V Specification 13 Dec 2019 Chapter 16 pg. 97
-// *** probably need more documentation in this file since the book is very light on decompression.
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/ifu/spill.sv

@@ -9,7 +9,7 @@
 //          cache line boundaries or if instruction address without a cache crosses
 //          XLEN/8 boundary.
 //
-// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/align.sv

@@ -9,7 +9,7 @@
 //          It is simlar to the IFU's spill module and probably could be merged together with 
 //          some effort.
 //
-// Documentation: RISC-V System on Chip Design Chapter 11 (Figure 11.5)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/amoalu.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Performs AMO operations
 // 
-// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/atomic.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Wrapper for amoalu and lrsc
 //
-// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/dtim.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: tightly integrated memory into the LSU.
 //
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/endianswap.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Swap byte order for Big-Endian accesses
 // 
-// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/lrsc.sv

@@ -8,7 +8,7 @@
 // Purpose: Load Reserved / Store Conditional unit
 //          Track the reservation and squash the store if it fails
 //
-// Documentation: RISC-V System on Chip Design Chapter 14 (Figure ***)
+// Documentation: RISC-V System on Chip Design
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/lsu.sv

@@ -9,7 +9,7 @@
 //          HPTW, DMMU, data cache, interface to external bus
 //          Atomic, Endian swap, and subword read/write logic
 //  
-// Documentation: RISC-V System on Chip Design Chapter 9 (Figure 9.2)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/subwordread.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Extract subwords and sign extend for reads
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/subwordwrite.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: Masking and muxing for subword writes
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/lsu/swbytemask.sv

@@ -7,7 +7,7 @@
 //
 // Purpose: On-chip RAM, external to core
 // 
-// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/mdu/div.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Restoring integer division using a shift register and subtractor
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/mdu/divstep.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Radix-2 restoring integer division step.  k steps are used in div
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.19)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/mdu/mdu.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: M extension multiply and divide
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.21)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw

src/mdu/mul.sv

@@ -6,7 +6,7 @@
 //
 // Purpose: Integer multiplication
 // 
-// Documentation: RISC-V System on Chip Design Chapter 12 (Figure 12.18)
+// Documentation: RISC-V System on Chip Design
 //
 // A component of the CORE-V-WALLY configurable RISC-V project.
 // https://github.com/openhwgroup/cvw