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Removed *** from IFU, lrcs.

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This commit is contained in:
Ross Thompson 2024-06-19 09:40:35 -07:00
parent c5dac4d775
commit ab1ee3d69b
5 changed files with 1 additions and 54 deletions
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1
fpga/src/fpgaTopArtyA7.sv
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@ -1048,7 +1048,6 @@ module fpgaTop
.sys_rst(resetn), // omg. this is active low?!?!??
.mmcm_locked(mmcm_locked),
// *** What are these?
.app_sr_req(1'b0), // reserved command
.app_ref_req(1'b0), // refresh command
.app_zq_req(1'b0), // recalibrate command

2
sim/vcs/run_vcs
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@ -86,7 +86,7 @@ INCLUDE_DIRS=$(find ${SRC} -type d | xargs -I {} echo -n "{} ")
INCLUDE_PATH="+incdir+${CFG}/${CONFIG_VARIANT} +incdir+${CFG}/deriv/${CONFIG_VARIANT} +incdir+${CFG}/shared +incdir+../../tests +define+ +incdir+${TB} ${SRC}/cvw.sv +incdir+${SRC}"
# Prepare RTL files avoiding certain paths
RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/clockgater.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv") ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")"
RTL_FILES="$INCLUDE_DIRS $(find ${SRC} -name "*.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x64.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_128x64.sv" ! -path "${SRC}/generic/mem/rom1p1r_128x32.sv" ! -path "${SRC}/generic/mem/ram2p1r1wbe_2048x64.sv") ${TB}/testbench.sv $(find ${TB}/common -name "*.sv" ! -path "${TB}/common/wallyTracer.sv")"
# Simulation and Coverage Commands
OUTPUT="sim_out"

1
src/ebu/buscachefsm.sv
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@ -128,7 +128,6 @@ module buscachefsm #(
assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK;
assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW) | BusCMOZero)) |
//(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem.
(CurrState == DATA_PHASE) |
(CurrState == ATOMIC_PHASE) |
(CurrState == ATOMIC_READ_DATA_PHASE) |

50
src/generic/clockgater.sv
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@ -1,50 +0,0 @@
///////////////////////////////////////////
// clockgater.sv
//
// Written: Ross Thompson 9 January 2021
// Modified:
//
// Purpose: Clock gater model. Must use standard cell for synthesis.
//
// A component of the CORE-V-WALLY configurable RISC-V project.
// https://github.com/openhwgroup/cvw
//
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
//
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
//
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
// may obtain a copy of the License at
//
// https://solderpad.org/licenses/SHL-2.1/
//
// Unless required by applicable law or agreed to in writing, any work distributed under the
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
// either express or implied. See the License for the specific language governing permissions
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
module clockgater #(parameter FPGA) (
input logic E,
input logic SE,
input logic CLK,
output logic ECLK
);
if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK));
else begin
// *** BUG
// VERY IMPORTANT.
// This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would.
// Do not use this in synthesis!
logic enable_q;
always_latch begin
if(~CLK) begin
enable_q <= E | SE;
end
end
assign ECLK = enable_q & CLK;
end
endmodule

1
src/lsu/lrsc.sv
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@ -45,7 +45,6 @@ module lrsc import cvw::*; #(parameter cvw_t P) (
localparam RESERVATION_SET_SIZE_IN_BYTES = P.XLEN/8;
localparam RESERVATION_SET_ADDRESS_BITS = $clog2(RESERVATION_SET_SIZE_IN_BYTES); // 2 for rv32, 3 for rv64
// possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
// Handle atomic load reserved / store conditional
logic [P.PA_BITS-1:RESERVATION_SET_ADDRESS_BITS] ReservationPAdrW;
logic ReservationValidM, ReservationValidW;