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Lint cleanup

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This commit is contained in:
David Harris 2024-06-20 00:10:03 -07:00
parent 5f1ee1ac85
commit 0ab3f28991
5 changed files with 21 additions and 8 deletions
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4
bin/lint-wally
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@ -12,7 +12,7 @@ NC='\033[0m' # No Color
fails=0
if [ "$1" == "--nightly" ]; then
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i) # fdqh_rv64gc
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i)
derivconfigs=`ls $WALLY/config/deriv`
for entry in $derivconfigs
do
@ -21,7 +21,7 @@ if [ "$1" == "--nightly" ]; then
fi
done
else
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i ) # add fdqh_rv64gc when working
configs=(rv32e rv64gc rv32gc rv32imc rv32i rv64i fdqh_rv64gc)
fi
for config in ${configs[@]}; do

13
config/derivlist.txt
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@ -388,10 +388,23 @@ VIRTMEM_SUPPORTED 0
deriv nodcache_rv32gc rv32gc
DCACHE_SUPPORTED 0
D_SUPPORTED 0
ZALRSC_SUPPORTED 0
ZAAMO_SUPPORTED 0
ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0
VIRTMEM_SUPPORTED 0
# nocache_rv32gc must also disable several features incompatible with no cache
deriv nocache_rv32gc rv32gc
ICACHE_SUPPORTED 0
DCACHE_SUPPORTED 0
D_SUPPORTED 0
ZALRSC_SUPPORTED 0
ZAAMO_SUPPORTED 0
ZICBOM_SUPPORTED 0
ZICBOZ_SUPPORTED 0
VIRTMEM_SUPPORTED 0
deriv noicache_rv64gc rv64gc
ICACHE_SUPPORTED 0

2
src/ieu/kmu/zknde64.sv
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@ -43,7 +43,7 @@ module zknde64 import cvw::*; #(parameter cvw_t P) (
aes64e aes64e(.rs1(A), .rs2(B), .finalround(ZKNSelect[2]), .Sbox0Out, .SboxEIn, .result(aes64eRes));
mux2 #(32) sboxmux(SboxEIn, SboxKIn, ZKNSelect[1], Sbox0In);
end else begin
assign aes64dRes = '0;
assign aes64eRes = '0;
assign Sbox0In = SboxKIn;
end

9
src/lsu/lsu.sv
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@ -144,7 +144,6 @@ module lsu import cvw::*; #(parameter cvw_t P) (
logic DTLBMissM; // DTLB miss causes HPTW walk
logic DTLBWriteM; // Writes PTE and PageType to DTLB
logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
logic LSULoadAccessFaultM; // Load acces fault
logic LSUStoreAmoAccessFaultM; // Store access fault
logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle
@ -194,13 +193,13 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if(P.VIRTMEM_SUPPORTED) begin : hptw
hptw #(P) hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissOrUpdateAF, .ITLBWriteF,
.DTLBMissOrUpdateDAM, .DTLBWriteM, .DataUpdateDAM,
.DTLBMissOrUpdateDAM, .DTLBWriteM,
.FlushW, .DCacheBusStallM, .SATP_REGW, .PCSpillF,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_ADUE, .PrivilegeModeW,
.ReadDataM(ReadDataM[P.XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
.WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
.IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM,
.IHAdrM, .HPTWStall, .SelHPTW,
.IHAdrM, .HPTWStall, .SelHPTW,
.IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM,
.LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF,
.LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF
@ -236,6 +235,8 @@ module lsu import cvw::*; #(parameter cvw_t P) (
if(P.ZICSR_SUPPORTED == 1) begin : dmmu
logic DisableTranslation; // During HPTW walk or D$ flush disable virtual memory address translation
logic WriteAccessM;
logic DataUpdateDAM; // DTLB hit needs to update dirty or access bits
assign DisableTranslation = SelHPTW | FlushDCacheM;
assign WriteAccessM = PreLSURWM[0];
mmu #(.P(P), .TLB_ENTRIES(P.DTLB_ENTRIES), .IMMU(0))
@ -245,7 +246,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
.PhysicalAddress(PAdrM), .TLBMiss(DTLBMissM), .Cacheable(CacheableM), .Idempotent(), .SelTIM(SelDTIM),
.InstrAccessFaultF(), .LoadAccessFaultM(LSULoadAccessFaultM),
.StoreAmoAccessFaultM(LSUStoreAmoAccessFaultM), .InstrPageFaultF(), .LoadPageFaultM(LSULoadPageFaultM),
.StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
.StoreAmoPageFaultM(LSUStoreAmoPageFaultM),
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
.UpdateDA(DataUpdateDAM), .CMOpM(CMOpM),
.AtomicAccessM(|LSUAtomicM), .ExecuteAccessF(1'b0),

1
src/mmu/hptw.sv
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@ -49,7 +49,6 @@ module hptw import cvw::*; #(parameter cvw_t P) (
input logic ITLBMissOrUpdateAF,
input logic DTLBMissOrUpdateDAM,
input logic FlushW,
input logic DataUpdateDAM,
output logic [P.XLEN-1:0] PTE, // page table entry to TLBs
output logic [1:0] PageType, // page type to TLBs
output logic ITLBWriteF, DTLBWriteM, // write TLB with new entry