Rose Thompson fc62f80407 Closer to fully working hardware tracer.		2024-06-04 11:31:05 -05:00
..
cache	Fixed the cache miss counter.	2024-04-24 16:14:51 -05:00
ebu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
fpu	Parameterized FMA. However, some offsets are not parameterized. See PR #793 for list of changes	2024-05-13 15:16:00 -07:00
generic	Fixed byte enables for synthesis	2024-04-27 06:25:24 -07:00
hazard	Successfully added RVVIStall for back pressure to slow down the pipeline if the ethernet or host computer running imperasDV can't keep up.	2024-05-22 09:56:12 -05:00
ieu	ZAAMO and ZALRSC implemented but not tested	2024-05-07 16:45:49 -07:00
ifu	Certain Zcb instructions are dependent on other extensions, not the entire extension	2024-05-15 19:16:43 -07:00
lsu	ZAAMO and ZALRSC implemented but not tested	2024-05-07 16:45:49 -07:00
mdu	Remove additional bitwise operator	2024-05-15 09:29:54 -07:00
mmu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
privileged	update config to derive MISA from macros	2024-05-14 06:49:18 -07:00
rvvi	Closer to fully working hardware tracer.	2024-06-04 11:31:05 -05:00
uncore	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
wally	Moved the rvvisynth code to testbench since I only want this for simulation and fpga.	2024-05-24 16:10:58 -05:00
cvw.sv	Merge pull request #798 from jordancarlin/newConfig	2024-05-15 10:28:44 -05:00