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changed intdivb width

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This commit is contained in:
Kevin Kim 2024-06-21 21:31:19 -07:00
parent 9a59c8e07f
commit 00bf3faa9c
2 changed files with 8 additions and 7 deletions
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5
src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -45,7 +45,8 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
output logic [P.XLEN-1:0] FIntDivResultM // U/Q(XLEN.0)
);
logic [P.DIVb+3:0] W, Sum;
logic [P.DIVb+3:0] Sum;
logic [P.INTDIVb+3:0] W;
logic [P.DIVb:0] PreUmM;
logic NegStickyM;
logic weq0E, WZeroM;
@ -105,7 +106,7 @@ module fdivsqrtpostproc import cvw::*; #(parameter cvw_t P) (
assign SumTrunc = Sum[P.DIVb+3:P.DIVb-P.INTDIVb];
assign DTrunc = D[P.DIVb+3:P.DIVb-P.INTDIVb];
assign W = $signed(Sum) >>> P.LOGR;
assign W = $signed(SumTrunc) >>> P.LOGR;
assign UnsignedQuotM = {3'b000, PreUmM[P.DIVb:P.DIVb-P.INTDIVb]};

10
testbench/tests.vh
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@ -1125,11 +1125,11 @@ string imperas32f[] = '{
"rv64i_m/M/src/divu-01.S",
"rv64i_m/M/src/divuw-01.S",
"rv64i_m/M/src/divw-01.S",
"rv64i_m/M/src/mul-01.S",
"rv64i_m/M/src/mulh-01.S",
"rv64i_m/M/src/mulhsu-01.S",
"rv64i_m/M/src/mulhu-01.S",
"rv64i_m/M/src/mulw-01.S",
//"rv64i_m/M/src/mul-01.S",
//"rv64i_m/M/src/mulh-01.S",
//"rv64i_m/M/src/mulhsu-01.S",
//"rv64i_m/M/src/mulhu-01.S",
//"rv64i_m/M/src/mulw-01.S",
"rv64i_m/M/src/rem-01.S",
"rv64i_m/M/src/remu-01.S",
"rv64i_m/M/src/remuw-01.S",