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Merge pull request #827 from davidharrishmc/dev

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Fixed support for individual crypto extensions without Zb*
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Rose Thompson 2024-06-06 09:31:07 -05:00 committed by GitHub
commit 5dfde808f0
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5 changed files with 22 additions and 14 deletions
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4
src/ieu/alu.sv
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@ -109,7 +109,9 @@ module alu import cvw::*; #(parameter cvw_t P) (
else assign PreALUResult = FullResult;
// Bit manipulation muxing
if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
if (P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED |
P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED |
P.ZKND_SUPPORTED | P.ZKNE_SUPPORTED | P.ZKNH_SUPPORTED) begin : bitmanipalu
bitmanipalu #(P) balu(
.A, .B, .W64, .BSelect, .ZBBSelect, .BMUActive,
.Funct3, .Funct7, .Rs2E, .LT,.LTU, .BALUControl, .PreALUResult, .FullResult,

7
src/ieu/bmu/bitmanipalu.sv
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@ -87,7 +87,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
end
// Bit reverse needed for some ZBB, ZBC instructions
if (P.ZBC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBB_SUPPORTED) begin: bitreverse
bitreverse #(P.XLEN) brA(.A(ABMU), .RevA);
end
@ -99,6 +99,11 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
// ZBB Unit
if (P.ZBB_SUPPORTED) begin: zbb
zbb #(P.XLEN) ZBB(.A(ABMU), .RevA, .B(BBMU), .W64, .LT, .LTU, .BUnsigned(Funct3[0]), .ZBBSelect(ZBBSelect[2:0]), .ZBBResult);
end else if (P.ZBKB_SUPPORTED) begin: zbkbonly // only needs rev8 portion
genvar i;
for (i=0;i<P.XLEN;i+=8) begin:byteloop
assign ZBBResult[P.XLEN-i-1:P.XLEN-i-8] = ABMU[i+7:i]; // Rev8
end
end else assign ZBBResult = '0;
// ZBKB Unit

13
src/ieu/bmu/bmuctrl.sv
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@ -98,10 +98,6 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
BMUControlsD = `BMUCTRLW'b000_0010_0001_1_1_0_1_0_0_0_0_0; // sign extend instruction
else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))
BMUControlsD = `BMUCTRLW'b000_0010_0000_1_1_0_1_0_0_0_0_0; // count instruction
// // coverage off: This case can't occur in RV64
// 17'b0110011_0000100_100: if (P.XLEN == 32)
// BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32)
// // coverage on
17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111)
BMUControlsD = `BMUCTRLW'b000_0010_0010_1_1_0_1_0_0_0_0_0; // orc.b
17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0010_0111_1_0_0_1_1_0_0_0_0; // max
@ -124,12 +120,13 @@ module bmuctrl import cvw::*; #(parameter cvw_t P) (
if (P.ZBC_SUPPORTED)
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000101_010: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulr
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // ZBC instruction
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul/clmulh
endcase
if (P.ZBKC_SUPPORTED | P.ZBC_SUPPORTED) begin
if (P.ZBKC_SUPPORTED) begin
casez({OpD, Funct7D, Funct3D})
17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul
17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh
17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul/clmulh
// 17'b0110011_0000101_001: BMUControlsD = `BMUCTRLW'b000_0011_0000_1_0_0_1_0_0_0_0_0; // clmul
// 17'b0110011_0000101_011: BMUControlsD = `BMUCTRLW'b000_0011_0001_1_0_0_1_0_0_0_0_0; // clmulh
endcase
end

8
src/ieu/controller.sv
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@ -175,7 +175,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
// Be rigorous about detecting illegal instructions if CSRs or bit manipulation or conditional ops are supported
// otherwise be cheap
if (P.ZICSR_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED | P.ZBS_SUPPORTED | P.ZICOND_SUPPORTED) begin:legalcheck // Exact integer decoding
if (P.ZICSR_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED | P.ZBS_SUPPORTED |
P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKNE_SUPPORTED |
P.ZKND_SUPPORTED | P.ZKNH_SUPPORTED | P.ZICOND_SUPPORTED) begin:legalcheck // Exact integer decoding
logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD;
logic Funct7ShiftZeroD, Funct7Shiftb5D;
@ -318,7 +320,9 @@ module controller import cvw::*; #(parameter cvw_t P) (
assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
// bit manipulation Configuration Block
if (P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
if (P.ZBS_SUPPORTED | P.ZBA_SUPPORTED | P.ZBB_SUPPORTED | P.ZBC_SUPPORTED |
P.ZBKB_SUPPORTED | P.ZBKC_SUPPORTED | P.ZBKX_SUPPORTED | P.ZKNE_SUPPORTED |
P.ZKND_SUPPORTED | P.ZKNH_SUPPORTED) begin: bitmanipi
logic IllegalBitmanipInstrD; // Unrecognized B instruction
logic BRegWriteD; // Indicates if it is a R type BMU instruction in decode stage
logic BW64D; // Indicates if it is a W type BMU instruction in decode stage

4
src/ieu/shifter.sv
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@ -40,7 +40,7 @@ module shifter import cvw::*; #(parameter cvw_t P) (
assign Sign = A[P.XLEN-1] & SubArith; // sign bit for sign extension
if (P.XLEN==32) begin // rv32
if (P.ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates
always_comb // funnel mux
case({Right, Rotate})
2'b00: Z = {A[31:0], 31'b0};
@ -57,7 +57,7 @@ module shifter import cvw::*; #(parameter cvw_t P) (
end else begin // rv64
logic [P.XLEN-1:0] A64;
mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux
if (P.ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
if (P.ZBB_SUPPORTED | P.ZBKB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates
// shifter rotate source select mux
logic [P.XLEN-1:0] RotA; // rotate source
mux2 #(P.XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons