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Updated spill logic to reflect changes in textbook.

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This commit is contained in:
Rose Thompson 2024-06-02 15:48:42 -05:00
parent 3da62558ec
commit 731e1fe08f
2 changed files with 3 additions and 3 deletions
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2
src/ifu/ifu.sv
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@ -148,7 +148,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
if(P.ZCA_SUPPORTED) begin : Spill
spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF,
spill #(P) spill(.clk, .reset, .StallF, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF,
.IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
end else begin : NoSpill
assign PCSpillNextF = PCNextF;

4
src/ifu/spill.sv
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@ -33,7 +33,7 @@
module spill import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic reset,
input logic StallD, FlushD,
input logic StallF, FlushD,
input logic [P.XLEN-1:0] PCF, // 2 byte aligned PC in Fetch stage
input logic [P.XLEN-1:2] PCPlus4F, // PCF + 4
input logic [P.XLEN-1:0] PCNextF, // The next PCF
@ -96,7 +96,7 @@ module spill import cvw::*; #(parameter cvw_t P) (
case (CurrState)
STATE_READY: if (TakeSpillF) NextState = STATE_SPILL;
else NextState = STATE_READY;
STATE_SPILL: if(StallD) NextState = STATE_SPILL;
STATE_SPILL: if(StallF) NextState = STATE_SPILL;
else NextState = STATE_READY;
default: NextState = STATE_READY;
endcase