Code cleanup

src/fpu/postproc/shiftcorrection.sv

@@ -51,7 +51,7 @@ module shiftcorrection import cvw::*;  #(parameter cvw_t P) (
   logic                            LeftShiftQm;            // should the divsqrt result be shifted one to the left
   logic                            RightShift;             // shift right by 1
 
-  // *** 4/16/24 this code is a mess and needs cleaning and explaining
+  // dh 4/16/24 this code is a mess and needs cleaning and explaining
   // define bit widths
   // seems to shift by 0, 1, or 2.  right and left shift is confusing
   

src/lsu/amoalu.sv

@@ -73,7 +73,7 @@ module amoalu import cvw::*;  #(parameter cvw_t P) (
       5'b10100: y = cmp ? a : b; // amomax
       5'b11000: y = cmp ? a : b; // amominu
       5'b11100: y = cmp ? a : b; // amomaxu
-      default:  y = 'x;          // undefined; *** could change to b for efficiency
+      default:  y = 'x;          // undefined
     endcase
 
   // sign extend output if necessary for w64

src/privileged/csrsr.sv

@@ -66,7 +66,7 @@ module csrsr import cvw::*;  #(parameter cvw_t P) (
                            STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
                            STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
                           /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
-    assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value.  Spec is not clear what it should be.
+    assign MSTATUSH_REGW = '0; // does not exist when XLEN=64, and accessing will throw an illegal instruction
   end else begin: csrsr32 // RV32
     assign MSTATUS_REGW  = {STATUS_SD, 8'b0,
                            STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,

src/uncore/clint_apb.sv

@@ -85,7 +85,7 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
         if (entry == CLINT_MTIMECMP) begin
           for(i=0;i<P.XLEN/8;i++)
             if(PSTRB[i])
-              MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8]; // ***dh: this notation isn't in book yet - maybe from Ross
+              MTIMECMP[i*8 +: 8] <= PWDATA[i*8 +: 8];
         end
       end
 

studies/ppa/ppa.sv

@@ -693,8 +693,6 @@ module ppa_mux8_128 #(parameter WIDTH = 128) (
   assign y = s[2] ? (s[1] ? (s[0] ? d5 : d4) : (s[0] ? d6 : d7)) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); 
 endmodule
 
-// *** some way to express data-critical inputs
-
 module ppa_flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 

testbench/common/DCacheFlushFSM.sv

@@ -97,7 +97,7 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
                   // see https://verificationacademy.com/forums/systemverilog/range-must-be-bounded-constant-expressions
                   //ShadowRAM[CacheAdr[j][i][k] >> $clog2(P.XLEN/8)] = cacheline[P.XLEN*(k+1)-1:P.XLEN*k];
                   /* verilator lint_off WIDTHTRUNC */
-                  // *** lint error: address trunc warning for shadowram index
+                  // avoid lint error: address trunc warning for shadowram index
                   ShadowRAM[(CacheAdr[j][i][l] >> $clog2(P.XLEN/8)) + {{{P.PA_BITS-32}{1'b0}}, k}] = CacheData[j][i][l][P.XLEN*k +: P.XLEN];
                   /* verilator lint_on WIDTHTRUNC */
                 end