Rose Thompson 9471dcd296 Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. ... Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.		2024-07-19 17:08:47 -05:00
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cache	Signal name changes to match book.	2024-06-02 16:32:25 -05:00
ebu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
fpu	Modify Fround Tmask to work for X=1	2024-05-25 12:56:02 -07:00
generic	Fixed byte enables for synthesis	2024-04-27 06:25:24 -07:00
hazard	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
ieu	AES cleanup	2024-05-24 14:28:30 -07:00
ifu	Last of the branch predictor signal name updates.	2024-06-02 17:01:51 -05:00
lsu	Changed name CacheWriteData to WriteData.	2024-05-28 18:00:39 -05:00
mdu	Remove additional bitwise operator	2024-05-15 09:29:54 -07:00
mmu	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
privileged	Updated more signal names to match book.	2024-06-02 16:59:11 -05:00
rvvi	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
uncore	Defined bit sizes more precisely to help VCS lint and conform to coding style	2024-04-21 08:40:11 -07:00
wally	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00
cvw.sv	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.	2024-07-19 17:08:47 -05:00