Unused signal cleanup

bin/lint-wally

@@ -51,4 +51,5 @@ echo -e "${GREEN}All ${#configs[@]} lints run with no errors or warnings"
 # -I points to the include directory where files such as `include config.vh  are found
 
 # For more exhaustive (and sometimes spurious) warnings, add --Wall to the Verilator command
+# verilator --lint-only -Wall --quiet --top-module wallywrapper -Iconfig/shared -Iconfig/rv64gc src/cvw.sv testbench/wallywrapper.sv src/*/*.sv src/*/*/*.sv -Wno-UNUSEDPARAM -Wno-VARHIDDEN -Wno-GENUNNAMED -Wno-PINCONNECTEMPTY
 # Unfortunately, this produces a bunch of UNUSED and UNDRIVEN signal warnings in blocks that are configured to not exist.

src/ebu/ahbcacheinterface.sv

@@ -79,8 +79,7 @@ module ahbcacheinterface import cvw::*; #(
   logic [P.PA_BITS-1:0]         LocalHADDR;                             // Address after selecting between cached and uncached operation
   logic [AHBWLOGBWPL-1:0]     BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
   logic                       CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
-  logic [P.AHBW/8-1:0]          BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
-  logic [P.AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
+ logic [P.AHBW-1:0]            PreHWDATA;                              // AHB Address phase write data
   logic [P.PA_BITS-1:0]         PAdrZero;
 
   genvar                      index;
@@ -117,6 +116,8 @@ module ahbcacheinterface import cvw::*; #(
   if (READ_ONLY_CACHE) begin
     assign HWSTRB = '0;
   end else begin // compute byte mask for AHB transaction based on size and address.  AHBW may be different than LLEN
+    logic [P.AHBW/8-1:0]          BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
+     
     swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended());
     flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB);
   end

src/ifu/bpred/RASPredictor.sv

@@ -31,7 +31,7 @@
 module RASPredictor import cvw::*;  #(parameter cvw_t P)(
   input  logic             clk,
   input  logic             reset, 
-  input  logic             StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
+  input  logic             StallD, StallE, StallM, FlushD, FlushE, FlushM,
   input  logic             BPReturnWrongD,                      // Prediction class is wrong
   input  logic             ReturnD,
   input  logic             ReturnE, CallE,                  // Instr class

src/ifu/bpred/bpred.sv

@@ -163,7 +163,7 @@ module bpred import cvw::*;  #(parameter cvw_t P) (
     .BTBBranchF, .BPCallF, .BPReturnF, .BPJumpF, .BPBranchF, .IClassWrongM, .BPReturnWrongD);
 
   // Part 3 RAS
-  RASPredictor #(P) RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
+  RASPredictor #(P) RASPredictor(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
     .BPReturnF, .ReturnD, .ReturnE, .CallE,
     .BPReturnWrongD, .RASPCF, .PCLinkE);
 

src/mdu/mdu.sv

@@ -45,12 +45,6 @@ module mdu import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]        MDUResultM;                     // result after W truncation
   logic                     W64M;                           // W-type instruction
 
-  logic [P.XLEN-1:0]        AMDU, BMDU;                     // Gated inputs to MDU
-
-  // gate data inputs to MDU to only operate when MDU is active.
-  assign AMDU = ForwardedSrcAE & {P.XLEN{MDUActiveE}};
-  assign BMDU = ForwardedSrcBE & {P.XLEN{MDUActiveE}};
-
   // Multiplier
   mul #(P.XLEN) mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);