mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes.
Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.
This commit is contained in:
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commit
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.gitignore
vendored
1
.gitignore
vendored
@ -237,3 +237,4 @@ tests/functcov
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tests/functcov/*
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tests/functcov/*/*
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sim/vcs/simprofile*
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/fpga/rvvidaemon/rvvidaemon
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@ -56,6 +56,10 @@ EXT_MEM_RANGE 64'h0FFFFFFF
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SDC_SUPPORTED 1
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PLIC_SDC_ID 32'd20
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BPRED_SIZE 32'd12
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RVVI_SYNTH_SUPPORTED 1
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RVVI_INIT_TIME_OUT 32'd100000000
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RVVI_PACKET_DELAY 32'd350
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# The syn configurations are trimmed down for faster synthesis.
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deriv syn_rv32e rv32e
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@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
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// Memory synthesis configuration
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localparam logic USE_SRAM = 0;
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// debug tools
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localparam logic RVVI_SYNTH_SUPPORTED = 0;
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localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
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localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
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`include "config-shared.vh"
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@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd2;
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// Memory synthesis configuration
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localparam logic USE_SRAM = 0;
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// debug tools
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localparam logic RVVI_SYNTH_SUPPORTED = 0;
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localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
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localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
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`include "config-shared.vh"
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@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
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// Memory synthesis configuration
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localparam logic USE_SRAM = 0;
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// debug tools
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localparam logic RVVI_SYNTH_SUPPORTED = 0;
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localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
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localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
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`include "config-shared.vh"
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@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
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// Memory synthesis configuration
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localparam logic USE_SRAM = 0;
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// debug tools
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localparam logic RVVI_SYNTH_SUPPORTED = 0;
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localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
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localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
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`include "config-shared.vh"
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@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
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// Memory synthesis configuration
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localparam logic USE_SRAM = 0;
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// debug tools
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localparam logic RVVI_SYNTH_SUPPORTED = 0;
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localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
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localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
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`include "config-shared.vh"
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@ -225,4 +225,9 @@ localparam DIVCOPIES = 32'd4;
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// Memory synthesis configuration
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localparam logic USE_SRAM = 0;
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// debug tools
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localparam logic RVVI_SYNTH_SUPPORTED = 0;
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localparam [31:0] RVVI_INIT_TIME_OUT = 32'd4;
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localparam [31:0] RVVI_PACKET_DELAY = 32'd2;
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`include "config-shared.vh"
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@ -199,5 +199,8 @@ localparam cvw_t P = '{
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FPDUR : FPDUR,
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DURLEN : DURLEN,
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DIVb : DIVb,
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DIVBLEN : DIVBLEN
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DIVBLEN : DIVBLEN,
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RVVI_SYNTH_SUPPORTED : RVVI_SYNTH_SUPPORTED,
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RVVI_INIT_TIME_OUT : RVVI_INIT_TIME_OUT,
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RVVI_PACKET_DELAY : RVVI_PACKET_DELAY
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};
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@ -513,7 +513,7 @@ module fpgaTop
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.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
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.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0),
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.GPIOIN, .GPIOOUT, .GPIOEN,
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.UARTSin, .UARTSout, .SDCIntr, .RVVIStall);
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.UARTSin, .UARTSout, .SDCIntr, .ExternalStall(RVVIStall));
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// ahb lite to axi bridge
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@ -1116,10 +1116,89 @@ module fpgaTop
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.device_temp(device_temp));
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localparam MAX_CSRS = 3;
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localparam TOTAL_CSRS = 36;
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// pipeline controlls
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logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
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// required
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logic [P.XLEN-1:0] PCM;
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logic InstrValidM;
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logic [31:0] InstrRawD;
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logic [63:0] Mcycle, Minstret;
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logic TrapM;
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logic [1:0] PrivilegeModeW;
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// registers gpr and fpr
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logic GPRWen, FPRWen;
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logic [4:0] GPRAddr, FPRAddr;
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logic [P.XLEN-1:0] GPRValue, FPRValue;
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logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
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(* mark_debug = "true" *) logic valid;
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logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
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rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .valid, .rvvi);
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assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
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assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
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assign StallW = fpgaTop.wallypipelinedsoc.core.StallW;
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assign FlushE = fpgaTop.wallypipelinedsoc.core.FlushE;
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assign FlushM = fpgaTop.wallypipelinedsoc.core.FlushM;
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assign FlushW = fpgaTop.wallypipelinedsoc.core.FlushW;
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assign InstrValidM = fpgaTop.wallypipelinedsoc.core.ieu.InstrValidM;
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assign InstrRawD = fpgaTop.wallypipelinedsoc.core.ifu.InstrRawD;
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assign PCM = fpgaTop.wallypipelinedsoc.core.ifu.PCM;
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assign Mcycle = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
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assign Minstret = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
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assign TrapM = fpgaTop.wallypipelinedsoc.core.TrapM;
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assign PrivilegeModeW = fpgaTop.wallypipelinedsoc.core.priv.priv.privmode.PrivilegeModeW;
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assign GPRAddr = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.a3;
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assign GPRWen = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.we3;
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assign GPRValue = fpgaTop.wallypipelinedsoc.core.ieu.dp.regf.wd3;
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assign FPRAddr = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.a4;
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assign FPRWen = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.we4;
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assign FPRValue = fpgaTop.wallypipelinedsoc.core.fpu.fpu.fregfile.wd4;
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assign CSRArray[0] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
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assign CSRArray[1] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
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assign CSRArray[2] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
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assign CSRArray[3] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
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assign CSRArray[4] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
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assign CSRArray[5] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
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assign CSRArray[6] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
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assign CSRArray[7] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
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assign CSRArray[8] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
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assign CSRArray[9] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
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assign CSRArray[10] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
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assign CSRArray[11] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
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assign CSRArray[12] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
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assign CSRArray[13] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
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assign CSRArray[14] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
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assign CSRArray[15] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
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assign CSRArray[16] = 0; // 12'hF11
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assign CSRArray[17] = 0; // 12'hF12
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assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
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assign CSRArray[19] = 0; // 12'hF15
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assign CSRArray[20] = 0; // 12'h34A
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// supervisor CSRs
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assign CSRArray[21] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
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assign CSRArray[22] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
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assign CSRArray[23] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
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assign CSRArray[24] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
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assign CSRArray[25] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
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assign CSRArray[26] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
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assign CSRArray[27] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
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assign CSRArray[28] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
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assign CSRArray[29] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
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assign CSRArray[30] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
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assign CSRArray[31] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
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assign CSRArray[32] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
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// user CSRs
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assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
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assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
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assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
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rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
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.PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM,
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.PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
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.valid, .rvvi);
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// axi 4 write data channel
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(* mark_debug = "true" *) logic [31:0] RvviAxiWdata;
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@ -193,7 +193,7 @@ set temp3 [lindex $PlusArgs 3]
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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vlog -lint -work ${WKDIR} +incdir+${CONFIG}/${CFG} +incdir+${CONFIG}/deriv/${CFG} +incdir+${CONFIG}/shared ${lockstepvoptstring} ${FCdefineIDV_INCLUDE_TRACE2COV} ${FCdefineINCLUDE_TRACE2COV} ${ImperasPubInc} ${ImperasPrivInc} ${rvviFiles} ${idvFiles} ${FCdefineCOVER_BASE_RV64I} ${FCdefineCOVER_LEVEL_DV_PR_EXT} ${FCdefineCOVER_RV64I} ${FCdefineCOVER_RV64M} ${FCdefineCOVER_RV64A} ${FCdefineCOVER_RV64F} ${FCdefineCOVER_RV64D} ${FCdefineCOVER_RV64ZICSR} ${FCdefineCOVER_RV64C} ${riscvISACOVsrc} ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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@ -25,7 +25,7 @@ TARGET=$(WORKING_DIR)/target
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# INCLUDE_PATH are pathes that Verilator should search for files it needs
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INCLUDE_PATH="-I${WALLY}/config/shared" "-I${WALLY}/config/$(WALLYCONF)" "-I${WALLY}/config/deriv/$(WALLYCONF)"
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# SOURCES are source files
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SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv
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SOURCES=${WALLY}/src/cvw.sv ${WALLY}/testbench/${TESTBENCH}.sv ${WALLY}/testbench/common/*.sv ${WALLY}/src/*/*.sv ${WALLY}/src/*/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*.sv ${WALLY}/addins/verilog-ethernet/*/*/*/*.sv
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# DEPENDENCIES are configuration files and source files, which leads to recompilation of executables
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DEPENDENCIES=${WALLY}/config/shared/*.vh $(SOURCES)
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@ -45,7 +45,7 @@ default: run
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run: wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH}
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mkdir -p $(VERILATOR_DIR)/logs
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wkdir/$(WALLYCONF)_$(TEST)/V${TESTBENCH} ${ARGTEST}
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profile: obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF)
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$(VERILATOR_DIR)/obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF) ${ARGTEST}
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mv gmon.out gmon_$(WALLYCONF).out
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@ -82,4 +82,4 @@ obj_dir_profiling/V${TESTBENCH}_$(WALLYCONF): $(DEPENDENCIES)
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$(SOURCES)
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clean:
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rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling
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rm -rf $(VERILATOR_DIR)/wkdir $(VERILATOR_DIR)/obj_dir_profiling $(VERILATOR_DIR)/logs $(VERILATOR_DIR)/logs_profiling
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@ -294,6 +294,11 @@ typedef struct packed {
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int DURLEN ;
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int DIVb ;
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int DIVBLEN ;
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// debug tools
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logic RVVI_SYNTH_SUPPORTED;
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logic [31:0] RVVI_INIT_TIME_OUT;
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logic [31:0] RVVI_PACKET_DELAY;
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} cvw_t;
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endpackage
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@ -31,7 +31,7 @@ module hazard import cvw::*; #(parameter cvw_t P) (
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input logic BPWrongE, CSRWriteFenceM, RetM, TrapM,
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input logic StructuralStallD,
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input logic LSUStallM, IFUStallF,
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input logic FPUStallD, RVVIStall,
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input logic FPUStallD, ExternalStall,
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input logic DivBusyE, FDivBusyE,
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input logic wfiM, IntPendingM,
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// Stall & flush outputs
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@ -89,7 +89,7 @@ module hazard import cvw::*; #(parameter cvw_t P) (
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// Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1.
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// assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause;
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// Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out.
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assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | RVVIStall;
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assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause) | ExternalStall;
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// Stall each stage for cause or if the next stage is stalled
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// coverage off: StallFCause is always 0
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@ -100,11 +100,8 @@ module packetizer import cvw::*; #(parameter cvw_t P,
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// have to count at least 250 ms after reset pulled to wait for the phy to actually be ready
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// at 20MHz 250 ms is 250e-3 / (1/20e6) = 5,000,000.
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counter #(32) rstcounter(m_axi_aclk, RstCountRst, RstCountEn, RstCount);
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assign CountFlag = RstCount == 32'd100000000;
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//assign CountFlag = RstCount == 32'd10;
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//assign DelayFlag = RstCount == 32'd800;
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assign DelayFlag = RstCount == 32'd350;
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//assign DelayFlag = RstCount == 32'd0;
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assign CountFlag = RstCount == P.RVVI_INIT_TIME_OUT;
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assign DelayFlag = RstCount == P.RVVI_PACKET_DELAY;
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counter #(32) framecounter(m_axi_aclk, ~m_axi_aresetn, (RvviAxiWready & RvviAxiWlast), FrameCount);
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@ -27,32 +27,38 @@
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`define FPGA 1
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`define FPGA 0
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module rvvisynth import cvw::*; #(parameter cvw_t P,
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parameter integer MAX_CSRS)(
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parameter integer MAX_CSRS, TOTAL_CSRS = 36)(
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input logic clk, reset,
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input logic StallE, StallM, StallW, FlushE, FlushM, FlushW,
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// required
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input logic [P.XLEN-1:0] PCM,
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input logic InstrValidM,
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input logic [31:0] InstrRawD,
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input logic [63:0] Mcycle, Minstret,
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input logic TrapM,
|
||||
input logic [1:0] PrivilegeModeW,
|
||||
// registers gpr and fpr
|
||||
input logic GPRWen, FPRWen,
|
||||
input logic [4:0] GPRAddr, FPRAddr,
|
||||
input logic [P.XLEN-1:0] GPRValue, FPRValue,
|
||||
input logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0],
|
||||
output logic valid,
|
||||
output logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi
|
||||
);
|
||||
|
||||
localparam TOTAL_CSRS = 36;
|
||||
|
||||
// pipeline controlls
|
||||
logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
|
||||
|
||||
// required
|
||||
logic [P.XLEN-1:0] PCM, PCW;
|
||||
logic InstrValidM, InstrValidW;
|
||||
logic [31:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
|
||||
logic [63:0] Mcycle, Minstret;
|
||||
logic TrapM, TrapW;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
logic [P.XLEN-1:0] PCW;
|
||||
logic InstrValidW;
|
||||
logic [31:0] InstrRawE, InstrRawM, InstrRawW;
|
||||
logic TrapW;
|
||||
|
||||
// registers gpr and fpr
|
||||
logic GPRWen, FPRWen;
|
||||
logic [4:0] GPRAddr, FPRAddr;
|
||||
logic [P.XLEN-1:0] GPRValue, FPRValue;
|
||||
logic [P.XLEN-1:0] XLENZeros;
|
||||
logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
|
||||
logic [TOTAL_CSRS-1:0] CSRArrayWen;
|
||||
logic [P.XLEN-1:0] CSRValue [MAX_CSRS-1:0];
|
||||
logic [TOTAL_CSRS-1:0] CSRWen [MAX_CSRS-1:0];
|
||||
@ -61,10 +67,11 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
|
||||
logic [11:0] CSRCount;
|
||||
logic [177+P.XLEN-1:0] Required;
|
||||
logic [10+2*P.XLEN-1:0] Registers;
|
||||
logic [MAX_CSRS*(P.XLEN+12)-1:0] CSRs;
|
||||
logic [MAX_CSRS*(P.XLEN+12)-1:0] CSRs;
|
||||
|
||||
// get signals from the core.
|
||||
if (`FPGA) begin
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign StallE = fpgaTop.wallypipelinedsoc.core.StallE;
|
||||
assign StallM = fpgaTop.wallypipelinedsoc.core.StallM;
|
||||
assign StallW = fpgaTop.wallypipelinedsoc.core.StallW;
|
||||
@ -123,7 +130,9 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
|
||||
assign CSRArray[33] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
|
||||
assign CSRArray[34] = fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
|
||||
assign CSRArray[35] = {fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FRM_REGW, fpgaTop.wallypipelinedsoc.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
end else begin // if (`FPGA)
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
assign StallE = dut.core.StallE;
|
||||
assign StallM = dut.core.StallM;
|
||||
assign StallW = dut.core.StallW;
|
||||
@ -182,6 +191,7 @@ module rvvisynth import cvw::*; #(parameter cvw_t P,
|
||||
assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
|
||||
assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
|
||||
assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
end
|
||||
|
||||
//
|
||||
|
@ -45,7 +45,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
output logic [3:0] HPROT,
|
||||
output logic [1:0] HTRANS,
|
||||
output logic HMASTLOCK,
|
||||
input logic RVVIStall
|
||||
input logic ExternalStall
|
||||
);
|
||||
|
||||
logic StallF, StallD, StallE, StallM, StallW;
|
||||
@ -275,7 +275,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) (
|
||||
.BPWrongE, .CSRWriteFenceM, .RetM, .TrapM,
|
||||
.StructuralStallD,
|
||||
.LSUStallM, .IFUStallF,
|
||||
.FPUStallD, .RVVIStall,
|
||||
.FPUStallD, .ExternalStall,
|
||||
.DivBusyE, .FDivBusyE,
|
||||
.wfiM, .IntPendingM,
|
||||
// Stall & flush outputs
|
||||
|
@ -37,7 +37,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
|
||||
output logic HSELEXT,
|
||||
output logic HSELEXTSDC,
|
||||
// fpga debug signals
|
||||
input logic RVVIStall,
|
||||
input logic ExternalStall,
|
||||
// outputs to external memory, shared with uncore memory
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [P.PA_BITS-1:0] HADDR,
|
||||
@ -77,7 +77,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
|
||||
wallypipelinedcore #(P) core(.clk, .reset,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT,
|
||||
.HRDATA, .HREADY, .HRESP, .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB,
|
||||
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .RVVIStall
|
||||
.HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .ExternalStall
|
||||
);
|
||||
|
||||
// instantiate uncore if a bus interface exists
|
||||
|
@ -261,11 +261,11 @@ module loggers import cvw::*; #(parameter cvw_t P,
|
||||
$fwrite(file, "BEGIN %s\n", memfilename);
|
||||
$fwrite(CFIfile, "BEGIN %s\n", memfilename);
|
||||
end
|
||||
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
|
||||
if(dut.core.ifu.IClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
|
||||
direction = PCSrcM ? "t" : "n";
|
||||
$fwrite(file, "%h %s\n", dut.core.PCM, direction);
|
||||
end
|
||||
if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
|
||||
if((|dut.core.ifu.IClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
|
||||
direction = PCSrcM ? "t" : "n";
|
||||
$fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
|
||||
end
|
||||
|
@ -580,7 +580,8 @@ module testbench;
|
||||
assign SDCIntr = 1'b0;
|
||||
end
|
||||
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .RVVIStall, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall(RVVIStall),
|
||||
.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HSELEXT, .HSELEXTSDC,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SDCIntr, .SPIIn, .SPIOut, .SPICS);
|
||||
@ -590,12 +591,91 @@ module testbench;
|
||||
clk = 1'b1; # 5; clk = 1'b0; # 5;
|
||||
end
|
||||
|
||||
if(`RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
|
||||
if(P.RVVI_SYNTH_SUPPORTED) begin : rvvi_synth
|
||||
localparam MAX_CSRS = 3;
|
||||
logic valid;
|
||||
logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvvi;
|
||||
|
||||
rvvisynth #(P, MAX_CSRS) rvvisynth(.clk, .reset, .valid, .rvvi);
|
||||
localparam TOTAL_CSRS = 36;
|
||||
|
||||
// pipeline controlls
|
||||
logic StallE, StallM, StallW, FlushE, FlushM, FlushW;
|
||||
// required
|
||||
logic [P.XLEN-1:0] PCM;
|
||||
logic InstrValidM;
|
||||
logic [31:0] InstrRawD;
|
||||
logic [63:0] Mcycle, Minstret;
|
||||
logic TrapM;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
// registers gpr and fpr
|
||||
logic GPRWen, FPRWen;
|
||||
logic [4:0] GPRAddr, FPRAddr;
|
||||
logic [P.XLEN-1:0] GPRValue, FPRValue;
|
||||
logic [P.XLEN-1:0] CSRArray [TOTAL_CSRS-1:0];
|
||||
|
||||
assign StallE = dut.core.StallE;
|
||||
assign StallM = dut.core.StallM;
|
||||
assign StallW = dut.core.StallW;
|
||||
assign FlushE = dut.core.FlushE;
|
||||
assign FlushM = dut.core.FlushM;
|
||||
assign FlushW = dut.core.FlushW;
|
||||
assign InstrValidM = dut.core.ieu.InstrValidM;
|
||||
assign InstrRawD = dut.core.ifu.InstrRawD;
|
||||
assign PCM = dut.core.ifu.PCM;
|
||||
assign Mcycle = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[0];
|
||||
assign Minstret = dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2];
|
||||
assign TrapM = dut.core.TrapM;
|
||||
assign PrivilegeModeW = dut.core.priv.priv.privmode.PrivilegeModeW;
|
||||
assign GPRAddr = dut.core.ieu.dp.regf.a3;
|
||||
assign GPRWen = dut.core.ieu.dp.regf.we3;
|
||||
assign GPRValue = dut.core.ieu.dp.regf.wd3;
|
||||
assign FPRAddr = dut.core.fpu.fpu.fregfile.a4;
|
||||
assign FPRWen = dut.core.fpu.fpu.fregfile.we4;
|
||||
assign FPRValue = dut.core.fpu.fpu.fregfile.wd4;
|
||||
|
||||
assign CSRArray[0] = dut.core.priv.priv.csr.csrm.MSTATUS_REGW; // 12'h300
|
||||
assign CSRArray[1] = dut.core.priv.priv.csr.csrm.MSTATUSH_REGW; // 12'h310
|
||||
assign CSRArray[2] = dut.core.priv.priv.csr.csrm.MTVEC_REGW; // 12'h305
|
||||
assign CSRArray[3] = dut.core.priv.priv.csr.csrm.MEPC_REGW; // 12'h341
|
||||
assign CSRArray[4] = dut.core.priv.priv.csr.csrm.MCOUNTEREN_REGW; // 12'h306
|
||||
assign CSRArray[5] = dut.core.priv.priv.csr.csrm.MCOUNTINHIBIT_REGW; // 12'h320
|
||||
assign CSRArray[6] = dut.core.priv.priv.csr.csrm.MEDELEG_REGW; // 12'h302
|
||||
assign CSRArray[7] = dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h303
|
||||
assign CSRArray[8] = dut.core.priv.priv.csr.csrm.MIP_REGW; // 12'h344
|
||||
assign CSRArray[9] = dut.core.priv.priv.csr.csrm.MIE_REGW; // 12'h304
|
||||
assign CSRArray[10] = dut.core.priv.priv.csr.csrm.MISA_REGW; // 12'h301
|
||||
assign CSRArray[11] = dut.core.priv.priv.csr.csrm.MENVCFG_REGW; // 12'h30A
|
||||
assign CSRArray[12] = dut.core.priv.priv.csr.csrm.MHARTID_REGW; // 12'hF14
|
||||
assign CSRArray[13] = dut.core.priv.priv.csr.csrm.MSCRATCH_REGW; // 12'h340
|
||||
assign CSRArray[14] = dut.core.priv.priv.csr.csrm.MCAUSE_REGW; // 12'h342
|
||||
assign CSRArray[15] = dut.core.priv.priv.csr.csrm.MTVAL_REGW; // 12'h343
|
||||
assign CSRArray[16] = 0; // 12'hF11
|
||||
assign CSRArray[17] = 0; // 12'hF12
|
||||
assign CSRArray[18] = {{P.XLEN-12{1'b0}}, 12'h100}; //P.XLEN'h100; // 12'hF13
|
||||
assign CSRArray[19] = 0; // 12'hF15
|
||||
assign CSRArray[20] = 0; // 12'h34A
|
||||
// supervisor CSRs
|
||||
assign CSRArray[21] = dut.core.priv.priv.csr.csrs.csrs.SSTATUS_REGW; // 12'h100
|
||||
assign CSRArray[22] = dut.core.priv.priv.csr.csrm.MIE_REGW & 12'h222; // 12'h104
|
||||
assign CSRArray[23] = dut.core.priv.priv.csr.csrs.csrs.STVEC_REGW; // 12'h105
|
||||
assign CSRArray[24] = dut.core.priv.priv.csr.csrs.csrs.SEPC_REGW; // 12'h141
|
||||
assign CSRArray[25] = dut.core.priv.priv.csr.csrs.csrs.SCOUNTEREN_REGW; // 12'h106
|
||||
assign CSRArray[26] = dut.core.priv.priv.csr.csrs.csrs.SENVCFG_REGW; // 12'h10A
|
||||
assign CSRArray[27] = dut.core.priv.priv.csr.csrs.csrs.SATP_REGW; // 12'h180
|
||||
assign CSRArray[28] = dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; // 12'h140
|
||||
assign CSRArray[29] = dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; // 12'h143
|
||||
assign CSRArray[30] = dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; // 12'h142
|
||||
assign CSRArray[31] = dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & dut.core.priv.priv.csr.csrm.MIDELEG_REGW; // 12'h144
|
||||
assign CSRArray[32] = dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // 12'h14D
|
||||
// user CSRs
|
||||
assign CSRArray[33] = dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; // 12'h001
|
||||
assign CSRArray[34] = dut.core.priv.priv.csr.csru.csru.FRM_REGW; // 12'h002
|
||||
assign CSRArray[35] = {dut.core.priv.priv.csr.csru.csru.FRM_REGW, dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW}; // 12'h003
|
||||
|
||||
rvvisynth #(P, MAX_CSRS, TOTAL_CSRS) rvvisynth(.clk, .reset, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.PCM, .InstrValidM, .InstrRawD, .Mcycle, .Minstret, .TrapM,
|
||||
.PrivilegeModeW, .GPRWen, .FPRWen, .GPRAddr, .FPRAddr, .GPRValue, .FPRValue, .CSRArray,
|
||||
.valid, .rvvi);
|
||||
|
||||
// axi 4 write data channel
|
||||
logic [31:0] RvviAxiWdata;
|
||||
@ -618,12 +698,11 @@ module testbench;
|
||||
.tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1),
|
||||
.rx_axis_tlast(), .rx_axis_tuser(),
|
||||
|
||||
// *** update these
|
||||
.mii_rx_clk(clk), // *** need to be the mii clock
|
||||
.mii_rx_clk(clk),
|
||||
.mii_rxd('0),
|
||||
.mii_rx_dv('0),
|
||||
.mii_rx_er('0),
|
||||
.mii_tx_clk(clk), // *** needs to be the mii clock
|
||||
.mii_tx_clk(clk),
|
||||
.mii_txd,
|
||||
.mii_tx_en,
|
||||
.mii_tx_er,
|
||||
|
@ -57,7 +57,7 @@ module wallywrapper;
|
||||
logic HREADY;
|
||||
logic HSELEXT;
|
||||
logic HSELEXTSDC;
|
||||
logic RVVIStall;
|
||||
logic ExternalStall;
|
||||
|
||||
// instantiate device to be tested
|
||||
assign GPIOIN = 0;
|
||||
@ -67,9 +67,9 @@ module wallywrapper;
|
||||
assign HRESPEXT = 0;
|
||||
assign HRDATAEXT = 0;
|
||||
|
||||
assign RVVIStall = '0;
|
||||
assign ExternalStall = '0;
|
||||
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .RVVIStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC,
|
||||
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .ExternalStall, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT, .HSELEXTSDC,
|
||||
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
|
||||
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
|
||||
.UARTSin, .UARTSout, .SPIIn, .SPIOut, .SPICS, .SDCIntr);
|
||||
|
Loading…
Reference in New Issue
Block a user