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https://github.com/openhwgroup/cvw
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Starting code cleanup
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@ -110,7 +110,7 @@ module ebu import cvw::*; #(parameter cvw_t P) (
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.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
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.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY));
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// output mux //*** switch to structural implementation
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// output mux
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assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0;
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assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0;
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assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.
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@ -190,7 +190,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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// shifter
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///////////////////////////////////////////////////////////////////////////
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// kill the shift if it's negative
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// kill the shift if it is negative
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// select the amount to shift by
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// fp -> int:
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// - shift left by CalcExp - essentially shifting until the unbiased exponent = 0
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@ -201,10 +201,10 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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// - shift left by LeadingZeros - to shift till the result is normalized
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// - only shift fp -> fp if the intital value is subnormal
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// - this is a problem because the input to the lzc was the fraction rather than the mantissa
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// - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
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// - rather have a few and-gates than an extra bit in the priority encoder???
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always_comb
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if(ToInt) ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}};
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else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
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else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
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else ShiftAmt = LeadingZeros;
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///////////////////////////////////////////////////////////////////////////
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@ -218,7 +218,6 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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{{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)},
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{2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
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assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10);
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// ***simplified from appearently redundant assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
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mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
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// Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z
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@ -46,9 +46,9 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
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bit [WIDTH-1:0] RAM[DEPTH-1:0];
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// ***************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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// TRUE SRAM macro
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// ***************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
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genvar index;
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// 64 x 128-bit SRAM
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@ -79,9 +79,9 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
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.A(addr), .D(din),
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.BWEB(~BitWriteMask), .Q(dout));
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// ***************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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// READ first SRAM model
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// ***************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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end else begin: ram
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integer i;
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@ -48,9 +48,9 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
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localparam SRAMWIDTH = 32;
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localparam SRAMNUMSETS = SRAMWIDTH/WIDTH;
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// ***************************************************************************
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// TRUE Smem macro
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// ***************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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// TRUE SRAM macro
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///////////////////////////////////////////////////////////////////////////////
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if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
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@ -107,9 +107,9 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
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end else begin
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// ***************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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// READ first SRAM model
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// ***************************************************************************
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///////////////////////////////////////////////////////////////////////////////
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integer i;
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/*
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initial begin // initialize memory for simulation only; not needed because done in the testbench now
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