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Starting code cleanup

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This commit is contained in:
David Harris 2024-06-14 02:54:43 -07:00
parent 334b616d6f
commit 6789f32154
5 changed files with 13 additions and 14 deletions
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2
src/ebu/ebu.sv
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@ -110,7 +110,7 @@ module ebu import cvw::*; #(parameter cvw_t P) (
.HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
.HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYIn(HREADY));
// output mux //*** switch to structural implementation
// output mux
assign HADDR = LSUSelect ? LSUHADDROut : IFUSelect ? IFUHADDROut : '0;
assign HSIZE = LSUSelect ? LSUHSIZEOut : IFUSelect ? IFUHSIZEOut: '0;
assign HBURST = LSUSelect ? LSUHBURSTOut : IFUSelect ? IFUHBURSTOut : '0; // If doing memory accesses, use LSUburst, else use Instruction burst.

6
src/fpu/fcvt.sv
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@ -190,7 +190,7 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
// shifter
///////////////////////////////////////////////////////////////////////////
// kill the shift if it's negative
// kill the shift if it is negative
// select the amount to shift by
// fp -> int:
// - shift left by CalcExp - essentially shifting until the unbiased exponent = 0
@ -201,10 +201,10 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
// - shift left by LeadingZeros - to shift till the result is normalized
// - only shift fp -> fp if the intital value is subnormal
// - this is a problem because the input to the lzc was the fraction rather than the mantissa
// - rather have a few and-gates than an extra bit in the priority encoder??? *** is this true?
// - rather have a few and-gates than an extra bit in the priority encoder???
always_comb
if(ToInt) ShiftAmt = Ce[P.LOGCVTLEN-1:0]&{P.LOGCVTLEN{~Ce[P.NE]}};
else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
else ShiftAmt = LeadingZeros;
///////////////////////////////////////////////////////////////////////////

1
src/fpu/fpu.sv
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@ -218,7 +218,6 @@ module fpu import cvw::*; #(parameter cvw_t P) (
{{P.FLEN-P.H_LEN{1'b1}}, 2'b0, {P.H_NE-1{1'b1}}, (P.H_NF)'(0)},
{2'b0, {P.NE-1{1'b1}}, (P.NF)'(0)}, FmtE, BoxedOneE); // NaN boxing zeroes
assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(PostProcSelE==2'b10);
// ***simplified from appearently redundant assign FmaAddSubE = OpCtrlE[2]&OpCtrlE[1]&(FResSelE==2'b01)&(PostProcSelE==2'b10);
mux2 #(P.FLEN) fyaddmux (PreYE, BoxedOneE, FmaAddSubE, YE); // Force Y to be 1 for add/subtract
// Select NAN-boxed value of Z = 0.0 in proper format for FMA for multiply X*Y+Z

8
src/generic/mem/ram1p1rwbe.sv
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@ -46,9 +46,9 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
bit [WIDTH-1:0] RAM[DEPTH-1:0];
// ***************************************************************************
///////////////////////////////////////////////////////////////////////////////
// TRUE SRAM macro
// ***************************************************************************
///////////////////////////////////////////////////////////////////////////////
if ((USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray
genvar index;
// 64 x 128-bit SRAM
@ -79,9 +79,9 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE
.A(addr), .D(din),
.BWEB(~BitWriteMask), .Q(dout));
// ***************************************************************************
///////////////////////////////////////////////////////////////////////////////
// READ first SRAM model
// ***************************************************************************
///////////////////////////////////////////////////////////////////////////////
end else begin: ram
integer i;

10
src/generic/mem/ram2p1r1wbe.sv
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@ -48,9 +48,9 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
localparam SRAMWIDTH = 32;
localparam SRAMNUMSETS = SRAMWIDTH/WIDTH;
// ***************************************************************************
// TRUE Smem macro
// ***************************************************************************
///////////////////////////////////////////////////////////////////////////////
// TRUE SRAM macro
///////////////////////////////////////////////////////////////////////////////
if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin
@ -107,9 +107,9 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
end else begin
// ***************************************************************************
///////////////////////////////////////////////////////////////////////////////
// READ first SRAM model
// ***************************************************************************
///////////////////////////////////////////////////////////////////////////////
integer i;
/*
initial begin // initialize memory for simulation only; not needed because done in the testbench now