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1513 Commits

Author SHA1 Message Date
James Stine
5b1f9797f5 update part I on sbtm change 2021-07-19 07:59:27 -05:00
David Harris
8e01007d1c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 00:25:06 -04:00
Katherine Parry
c9180f4ebd FDIV and FSQRT passes when simulating in modelsim 2021-07-18 23:00:04 -04:00
bbracker
e4a50a5bb8 change memread testvectors to not left-shift bytes and half-words 2021-07-18 21:49:53 -04:00
David Harris
46ab609498 Updated FMA1 with parameterized size 2021-07-18 20:40:49 -04:00
bbracker
5e9dcb3f1c linux testbench progress 2021-07-18 18:47:40 -04:00
David Harris
ed64d37e65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-18 17:36:29 -04:00
David Harris
4f8f52f283 Added FLEN, NE, NF to config and started using these in FMA1 2021-07-18 17:28:25 -04:00
Katherine Parry
60dabb9094 fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
David Harris
8317be5aed Renamed pagetablewalker to hptw 2021-07-18 04:11:33 -04:00
David Harris
c75d70126f LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall 2021-07-18 03:51:30 -04:00
David Harris
3f7a3b280e HPTW: Simpliifieid PRegEn 2021-07-18 03:35:38 -04:00
David Harris
60bd27a40e Removed EndWalk signal and simplified TLBMissReg 2021-07-18 03:26:43 -04:00
Ross Thompson
14220684b6 Fixed bug with rv32a/WALLY-LRSC test in imperas. Minor issue. 2021-07-17 21:02:24 -05:00
Ross Thompson
009c5314b4 Fixed LRSC in 64bit version. 32bit version is broken. 2021-07-17 20:58:49 -05:00
David Harris
8bdf1eaf0f added lrsc.sv 2021-07-17 21:15:08 -04:00
David Harris
8d348dacce Started atomics 2021-07-17 21:11:41 -04:00
David Harris
574f7d9c32 moved subwordread to lsu 2021-07-17 20:37:20 -04:00
David Harris
e82374d19f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 20:01:23 -04:00
David Harris
9a86fc899b LSU cleanup 2021-07-17 20:01:03 -04:00
David Harris
d9750c16a5 Pushing HPTWPAdrM flop into LSUArb 2021-07-17 19:39:18 -04:00
David Harris
586341a41a Simplified VPN case statement 2021-07-17 19:34:01 -04:00
Ross Thompson
9cfbc4aec0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-17 18:27:44 -05:00
David Harris
35b7577be2 Finished HPTW TranslationPAdr simlification 2021-07-17 19:27:24 -04:00
Ross Thompson
1aac97030a Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before. 2021-07-17 18:26:29 -05:00
David Harris
2b1fdfbae2 Further TranslationVAdr simplification 2021-07-17 19:24:37 -04:00
David Harris
b785a20f90 Continued Translation Address Cleanup of TranslationPAdrMux 2021-07-17 19:16:56 -04:00
David Harris
fc88b3a693 Continued Translation Address Cleanup 2021-07-17 19:09:13 -04:00
David Harris
6536ef8dce Refining address interface between HPTW and LSU 2021-07-17 19:02:18 -04:00
David Harris
7b92e7e590 Fixed bad register in I-FSD-01 Imperas test. 2021-07-17 17:08:07 -04:00
David Harris
a67292b5f3 trap.sv comment cleanup 2021-07-17 16:01:07 -04:00
David Harris
c1c3249709 trap.sv cleanup 2021-07-17 15:57:10 -04:00
David Harris
af5e1f7f39 Finished removing PageTableEntry redundant signals from hptw 2021-07-17 15:50:52 -04:00
David Harris
e182cac9bc hptw: Removed NonBusTrapM from LSU 2021-07-17 15:24:26 -04:00
David Harris
2f81e4c70d hptw: Removed NonBusTrapM from LSU 2021-07-17 15:22:24 -04:00
David Harris
428a9c1ca3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 15:11:43 -04:00
David Harris
863e6e72d6 hptw: Propagating PageTableEntryF removal through IFU 2021-07-17 15:04:39 -04:00
David Harris
a855e0170e hptw: Propagating PageTableEntryF removal through LSU 2021-07-17 15:01:01 -04:00
bbracker
8d65d50085 separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
David Harris
d4eeabe355 hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE 2021-07-17 14:48:44 -04:00
bbracker
82fc766819 swapped out linux testbench signal names 2021-07-17 14:48:12 -04:00
bbracker
18fb282a37 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 14:46:38 -04:00
bbracker
4a3503281f swapped out linux testbench signal names 2021-07-17 14:46:18 -04:00
David Harris
86e04c080d hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states 2021-07-17 14:36:27 -04:00
David Harris
714eef4a1a hptw: Eliminated A and D bit faults while walking page table, per spec 2021-07-17 14:29:20 -04:00
David Harris
90c5312f85 hptw: Simplified TranslationVAdr calculation based just on DTLBWalk 2021-07-17 14:16:33 -04:00
David Harris
42aee1db30 hptw: renamed DTLBMissQ to DTLBWalk 2021-07-17 14:13:00 -04:00
David Harris
6f22e9a393 hptw: renamed ADRE to ADR 2021-07-17 14:02:59 -04:00
David Harris
3ce22a60b3 hptw: replaced PreviousWalkerState with a PageType FSM 2021-07-17 13:54:58 -04:00
David Harris
89fd653cc1 hptw: removed ITLBMissFQ 2021-07-17 13:44:08 -04:00
David Harris
87aa527de7 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ea2aa469a1 hptw: Simplifed out AnyTLBMiss 2021-07-17 12:07:51 -04:00
David Harris
784e6cf538 hptw: Renamed Memstore to MemWrite 2021-07-17 12:01:43 -04:00
David Harris
0a6622a6fb hptw: Merged RV32/64 FSMs 2021-07-17 11:55:24 -04:00
David Harris
cf0975c937 hptw: FSM simplification 2021-07-17 11:41:43 -04:00
David Harris
4469b5a4b3 hptw: default state should be unreachable 2021-07-17 11:33:16 -04:00
David Harris
9cee6c2281 hptw: factored Misaligned 2021-07-17 11:31:16 -04:00
David Harris
fa12727bbb hptw: factored HPTWRead 2021-07-17 11:25:59 -04:00
David Harris
708f8cc3a2 hptw: factored HPTWRead 2021-07-17 11:25:52 -04:00
David Harris
ef63e1ab52 hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
880aa1c03a HPTW: more cleanup 2021-07-17 04:55:01 -04:00
David Harris
a0f6c9aec1 HPTW: factored out DTLBWrite/ITLBWrite 2021-07-17 04:44:23 -04:00
David Harris
08e494dd7d HPTW: factored out PageTableENtry 2021-07-17 04:40:01 -04:00
David Harris
bd270acdb6 more cleaning up FSM 2021-07-17 04:35:51 -04:00
David Harris
6d8a6eeba0 cleaning up FSM 2021-07-17 04:26:41 -04:00
David Harris
330e500442 Simplify FSM 2021-07-17 04:12:31 -04:00
David Harris
03ef3f7f17 Pulled TranslationPAdr mux out of HPTW FSM 2021-07-17 04:06:26 -04:00
David Harris
5698433463 Simplified bad PTE detection 2021-07-17 03:30:17 -04:00
David Harris
ac67342dd4 Pulled out shared PTEReg 2021-07-17 03:21:09 -04:00
David Harris
86ca9abe42 Flip-flop clean-up 2021-07-17 03:15:47 -04:00
David Harris
9a15a2f7df Flip-flop clean-up 2021-07-17 03:12:24 -04:00
David Harris
8241dd4599 Flip-flop clean-up 2021-07-17 03:10:17 -04:00
David Harris
a8a5fa4b3c Started pagetablewalker cleanup: combined state flops shared for both RV versions 2021-07-17 02:53:52 -04:00
David Harris
b65788d165 Replaced separate PageTypeF and PageTypeM with common PageType 2021-07-17 02:31:23 -04:00
David Harris
dac22d5016 Removed more unused signals from ahblite 2021-07-17 02:21:54 -04:00
David Harris
a898bbb991 Removed rest of HRDATAW from ahblite 2021-07-17 02:15:24 -04:00
David Harris
a19d3f126f Commented out HRDATAW logic in ebu 2021-07-17 02:10:57 -04:00
David Harris
e3dc59c5a2 renamed or_rows.sv 2021-07-16 20:17:03 -04:00
David Harris
1bd5c137a6 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Kip Macsai-Goren
d10fd25c33 included virtual memory tests in testbench 2021-07-16 17:57:24 -04:00
Ross Thompson
0b3dc288ec Made furture progress in the mmu tests. 2021-07-16 15:56:06 -05:00
Ross Thompson
5e18a15a4c Added guide for Ben to do linux conversion. 2021-07-16 15:04:30 -05:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
1aabee0478 Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Ross Thompson
b3bf04d474 Updated wave file. 2021-07-16 12:34:37 -05:00
Ross Thompson
46bce70e42 Fixed walker fault interaction with dcache. 2021-07-16 12:22:13 -05:00
bbracker
b0fcfc2773 reduce number of UART ports to 1 2021-07-16 12:42:29 -04:00
bbracker
01ca22af49 changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 12:27:15 -04:00
Ross Thompson
e0f719d513 Updated the ptw, lsuarb and dcache to hopefully solve the interlock issues. 2021-07-16 11:12:57 -05:00
bbracker
ae7d48c326 incremental linux config de-bloating 2021-07-16 12:08:58 -04:00
bbracker
40352ab7e4 incremental linux config de-bloating 2021-07-16 11:33:11 -04:00
bbracker
b1fe4ff295 incremental linux config de-bloating 2021-07-16 11:15:25 -04:00
bbracker
f34e28d187 incremental linux config de-bloating 2021-07-16 01:58:21 -04:00
bbracker
3bcc5808d4 incremental linux config de-bloating 2021-07-16 01:54:36 -04:00
bbracker
ff90e6744c incremental linux config de-bloating 2021-07-16 01:43:16 -04:00
bbracker
ca5a1755f3 incremental linux config de-bloating 2021-07-16 01:33:51 -04:00
bbracker
b003c651be incremental linux config de-bloating 2021-07-16 01:25:41 -04:00
bbracker
ae886b015d incremental linux config de-bloating 2021-07-16 01:00:12 -04:00
bbracker
7340e089f7 incremental linux config de-bloating 2021-07-16 00:46:22 -04:00
bbracker
c4716af4d6 incremental linux config de-bloating 2021-07-16 00:41:18 -04:00
bbracker
0238b869fb incremental linux config de-bloating 2021-07-16 00:34:41 -04:00
bbracker
3273b030e1 incremental linux config de-bloating 2021-07-16 00:16:12 -04:00
bbracker
66bf2005fe incremental linux config de-bloating 2021-07-16 00:10:31 -04:00
bbracker
4734f0eee5 incremental linux config de-bloating 2021-07-15 23:53:15 -04:00
bbracker
e565adfece incremental linux config de-bloating 2021-07-15 23:30:24 -04:00
bbracker
3ff723493f incremental linux config de-bloating 2021-07-15 23:12:21 -04:00
bbracker
8586462ee5 incremental linux config de-bloating 2021-07-15 23:00:20 -04:00
bbracker
03e0bdaa5a incremental linux config de-bloating 2021-07-15 21:33:52 -04:00
bbracker
e922732fc5 incremental linux config de-bloating 2021-07-15 20:54:36 -04:00
bbracker
c2535308fd working linux config 2021-07-15 18:49:54 -04:00
Kip Macsai-Goren
abd5b1c02d Still broken, midway through fixing understanding of how ptw and datacache interact in time especially wrt adrE, adrM, faults, and tlb interaction. 2021-07-15 18:30:29 -04:00
bbracker
3b6291b734 stripped down busybox a bit 2021-07-15 16:07:56 -04:00
Ross Thompson
e5d624c1fa Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
fa26aec588 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
fd1de6b047 Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
b9902b0560 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
8610ef204c Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Ross Thompson
704f4f724e dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
ba1e1ec231 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
c79650b508 Added d cache StallW checks for any time the cache wants to go to STATE_READY. 2021-07-14 17:25:50 -05:00
Ross Thompson
2c946a282f Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Katherine Parry
f5bfdf46db fpu unpacking unit created 2021-07-14 17:56:49 -04:00
Ross Thompson
e91501985c Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
adce800041 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. 2021-07-14 15:47:38 -05:00
Ross Thompson
d78e31e9df Forgot to include one hot decoder. 2021-07-14 15:46:52 -05:00
Ross Thompson
f4295ff097 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00
bbracker
335afb14e7 testvector unlinker for dev purposes 2021-07-14 11:05:34 -04:00
James Stine
e6d19be87c put back for now to test fdiv 2021-07-14 06:48:29 -05:00
bbracker
46e704b7ef Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 00:21:39 -04:00
bbracker
92899b33f8 make testvector scripts agree with new file structure; use symbols to determine end of linux boot 2021-07-14 00:21:29 -04:00
Ross Thompson
9b756d6a94 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
e8bf502bc2 Added CommitedM to data cache output. 2021-07-13 22:43:42 -05:00
bbracker
28887bb3d5 needed to create a directory for gdb script 2021-07-13 19:39:57 -04:00
Ross Thompson
3e57c899a2 Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
James E. Stine
46001fef27 mod 2 of fpdivsqrt update 2021-07-13 16:59:17 -04:00
James E. Stine
8382a17969 Update fpdivsqrt item until move into uarch 2021-07-13 16:53:20 -04:00
bbracker
f2bf4920d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 16:16:04 -04:00
bbracker
64d22753b5 changed QEMU to use different ports 2021-07-13 16:15:51 -04:00
Ross Thompson
baa2b5d15f Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
3c1a717399 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
32f27cfecf Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
afc1bc9c38 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
9de97c1e20 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Ross Thompson
47e16f5629 Fixed back to back store issue. 
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
 2021-07-13 12:46:20 -05:00
David Harris
2ba82d1a5c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
223086ac33 added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
ca19b2e215 Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
93d6688c3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
b5dddec858 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
3565580f40 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
Ross Thompson
224e3b2991 Fixed subword write. subword read should not feed into subword write. 2021-07-13 11:21:44 -05:00
Ross Thompson
30b7c4436c restored rv64ic config back to full sized dtim. 2021-07-13 11:18:54 -05:00
Ross Thompson
3951eb56f5 Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00
Ross Thompson
e594eb540d Got the shadow ram cache flush working. 2021-07-13 10:03:47 -05:00
bbracker
99587f58f7 whoops I accidentally made main.config into a symbolic link; now it is a source file 2021-07-13 11:00:01 -04:00
bbracker
fab906821a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 10:04:13 -04:00
bbracker
4b615c1564 working config for a buildroot that boots 2021-07-13 10:04:09 -04:00
David Harris
861ef5e1cb Replaced .or with or_rows structural code in MMU read circuitry for synthesis. 2021-07-13 09:32:02 -04:00
Ross Thompson
49f6eec579 Team work on solving the dcache data inconsistency problem. 2021-07-12 23:46:32 -05:00
Ross Thompson
ecc9b5006e Now updates the dtim with the dirty data in the dcache. 
Simulation is showing issues.  It lookslike the cache is not
evicting the correct data.
 2021-07-12 15:13:27 -05:00
Ross Thompson
1cc258ade1 Progress towards the test bench flush. 2021-07-12 14:22:13 -05:00
Katherine Parry
f3ac46df86 fcvt.sv cleanup 2021-07-11 21:30:01 -04:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
bbracker
6bd0ca673c rootfs.cpio no longer overlaps 2021-07-11 05:11:12 -04:00
Ross Thompson
f26d635614 Fixed the spurious AHB requests to address 0. Somehow by not having a default 
(else) in the fsm branch selection for STATE_READY in the d cache it was
possible to take an invalid branch through the fsm.
 2021-07-10 22:34:47 -05:00
Ross Thompson
fed7042fd9 Loads are working. 
There is a bug when the icache stalls 1 cycle before the d cache.
 2021-07-10 22:15:44 -05:00
Ross Thompson
60ed023734 Actually writes the correct data now on stores. 2021-07-10 17:48:47 -05:00
Ross Thompson
efe37ea079 Write miss with eviction works. 2021-07-10 15:17:40 -05:00
Ross Thompson
d65c01bc29 Write Hits and Write Misses without eviction are working correctly! The next 
step is to add eviction of dirty lines.
 2021-07-10 10:56:25 -05:00
bbracker
feaeeaf6ac greatly stripped down unused stuff in linux config 2021-07-10 11:53:35 -04:00
David Harris
20f2a4e47c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 19:18:35 -04:00
David Harris
d3ab6b192a added missing tlbmixer.sv 2021-07-09 19:18:23 -04:00
bbracker
3be73695e3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 18:56:28 -04:00
bbracker
2a54f6f242 fix_mem.py bugfix 2021-07-09 18:56:17 -04:00
Ross Thompson
b1ceeb40df Loads in modelsim, but the first store double does not function correctly. The write address is wrong so the cache is updated using the wrong address. 
I think this is do to the cycle latency of stores.  We probably need extra muxes to select between MemPAdrM and MemPAdrW depending on if the write is a
full cache block or a word write from the CPU.
 2021-07-09 17:14:54 -05:00
bbracker
1f52a2f938 organize/update buildroot scripts for new image 2021-07-09 17:03:47 -04:00
Ross Thompson
4c0cee1c19 Design loads in modelsim, but trap is an X. 2021-07-09 15:37:16 -05:00
Ross Thompson
ec80cc1820 Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented. 
Also faults and the dcache ptw interlock are not implemented.
 2021-07-09 15:16:38 -05:00
David Harris
39bd7e7edc Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-09 07:53:30 -04:00
David Harris
5c2f774c35 Simplified tlbmixer mux to and-or 2021-07-08 23:34:24 -04:00
David Harris
74b6d13195 Fixed missing stall in InstrRet counter 2021-07-08 20:08:04 -04:00
bbracker
44a48cf28d organize linux-testgen folder, add readme to describe Buildroot process, add Buildroot config source files 2021-07-08 19:18:11 -04:00
Ross Thompson
94c3fde724 Renamed signal in LSU toLSU and fromLSU to toDCache and fromDCache. 2021-07-08 18:03:52 -05:00
Ross Thompson
93aa39ca31 completed read miss branch through dcache fsm. 
The challenge now is to connect to ahb and lsu.
 2021-07-08 17:53:08 -05:00
David Harris
4f1a85ca7c Eliminate reserved bits from TLB RAM 2021-07-08 17:35:00 -04:00
David Harris
38772de21f Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram 2021-07-08 16:58:11 -04:00
David Harris
1190729896 TLB cleanup to match diagrams 2021-07-08 16:52:06 -04:00
Ross Thompson
910ddb83ae This d cache fsm is getting complex. 2021-07-08 15:26:16 -05:00
Ross Thompson
1fe06bc670 Partial implementation of the data cache. Missing the fsm. 2021-07-07 17:52:16 -05:00
David Harris
5d5274ec73 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-07 06:32:29 -04:00
David Harris
2bab3f769b Renamed tlb ReadLines to Matches 2021-07-07 06:32:26 -04:00
Abe
84711fbdc8 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
Abe
b757c96b2d Changed SvMode to SVMode on line 76 2021-07-06 23:28:58 -04:00
David Harris
af619dcd75 Added ASID matching for CAM 2021-07-06 18:56:25 -04:00
Kip Macsai-Goren
8350622f65 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd more TLB name touchups 2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
e08a578908 fixed upper bits page fault signal 2021-07-06 18:32:47 -04:00
David Harris
2e2aa2a972 connected signals in tlb by name instead of .* 2021-07-06 17:22:10 -04:00
David Harris
ee3a321002 changed tlbphysicalpagemask to structural 2021-07-06 17:16:58 -04:00
David Harris
f960561cbb changed tlbphysicalpagemask to structural 2021-07-06 17:08:04 -04:00
David Harris
032c38b7e7 MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB 2021-07-06 15:29:42 -04:00
Ross Thompson
412691df2d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 13:45:20 -05:00
Ross Thompson
3345ed7ff4 Merged several of the load/store/instruction access faults inside the mmu. 
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
 2021-07-06 13:43:53 -05:00
bbracker
d3dd70e3e6 more completely uncomment MMU tests to make sim wally work 2021-07-06 14:33:52 -04:00
Abe
8854532a79 Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140) 2021-07-06 12:37:58 -04:00
Ross Thompson
7af8cfba18 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-06 10:41:45 -05:00
Ross Thompson
6e7e318396 Fixed bug in the LSU pagetable walker interlock. 2021-07-06 10:41:36 -05:00
David Harris
b4082ba776 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:44:17 -04:00
David Harris
30fdd7abc8 Cleaned up tlb output muxing 2021-07-06 10:44:05 -04:00
David Harris
d58cad89a8 Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines 2021-07-06 10:38:30 -04:00
Kip Macsai-Goren
7e9961cac4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-06 10:16:34 -04:00
David Harris
694badcc6b Created tlbcontrol module to hide details 2021-07-06 03:25:11 -04:00
David Harris
f805aea236 Implemented TSR, TW, TVM, MXR status bits 2021-07-06 01:32:05 -04:00
David Harris
8b23162d6d Fixed adrdecs to use Access signals for TIMs 2021-07-05 23:42:58 -04:00
David Harris
71711c54c9 Don't generate HPTW when MEM_VIRTMEM=0 2021-07-05 23:35:44 -04:00
David Harris
179c8d3ed4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-05 23:23:17 -04:00
David Harris
6bac566bb7 Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
Ross Thompson
530ddd667b Fixed combo loop in the page table walker. 2021-07-05 16:37:26 -05:00
Ross Thompson
2a62ee2e70 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-05 16:07:27 -05:00
Kip Macsai-Goren
20cd0e208b added new mmu tests to makefrag and commented out in the testbench 2021-07-05 10:54:30 -04:00
David Harris
5f91b339aa Added F_SUPPORTED flag to disable floating point unit when not in MISA 2021-07-05 10:30:46 -04:00
David Harris
ac163e091c Fixed disabling MulDiv when not supported. Started adding generate for FPU unsupported 2021-07-04 19:33:46 -04:00
David Harris
004cac91e1 Simplified PLIC with generate 2021-07-04 19:17:15 -04:00
David Harris
0aae58abed Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 19:02:56 -04:00
David Harris
600e7802dd Renamed Funct3ToLSU/fromLSU -> SizeToLSU/FromLSU and simplified size muxing in lsuArb 2021-07-04 18:56:30 -04:00
David Harris
db5a06beaf Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 18:55:24 -04:00
David Harris
b23192cf1b Gave names to for loops in generate blocks for ease of reference 2021-07-04 18:52:16 -04:00
bbracker
287935c09d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 18:17:16 -04:00
David Harris
07f2064c19 Touched up TLB D and A bit checks 2021-07-04 18:17:09 -04:00
bbracker
ceac0352f7 ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF 2021-07-04 18:17:06 -04:00
Ross Thompson
b2c5c3f637 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 17:07:57 -05:00
David Harris
b0f199b574 Fixed TLB_ENTRIES merge conflict and handling of global PTEs 2021-07-04 18:05:22 -04:00
Ross Thompson
02721c29dc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:54:31 -05:00
Ross Thompson
17f37f21ff Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:53:16 -05:00
David Harris
8b707f7703 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:53:08 -04:00
David Harris
80666f0a71 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
Ross Thompson
a252416535 Removed the TranslationVAdrQ as it is not necessary. 2021-07-04 16:49:34 -05:00
bbracker
7191c03282 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-04 17:20:55 -04:00
bbracker
9c84ab436a for GPIO give priority to clearing interrupts 2021-07-04 17:20:16 -04:00
Ross Thompson
7f62808544 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-04 16:19:39 -05:00
David Harris
07ef67e537 Restructured TLB Read as AND-OR operation with one-hot match/read line 2021-07-04 17:01:22 -04:00
David Harris
8337d6df68 Reorganized TLB to use one-hot read/write select signals to eliminate decoders and encoders 2021-07-04 16:33:13 -04:00
David Harris
c281539f36 TLB cleanup 2021-07-04 14:59:04 -04:00
Ross Thompson
5b70eb86b0 relocated lsuarb and pagetable walker inside the lsu. Does not pass busybear or buildroot, but passes rv32ic and rv64ic. 2021-07-04 13:49:38 -05:00
David Harris
81742ef9e2 TLB cleanup 2021-07-04 14:37:53 -04:00
David Harris
152923e552 TLB minor organization 2021-07-04 14:30:56 -04:00
David Harris
7e22ae973e Fixed MPRV and MXR checks in TLB 2021-07-04 13:20:29 -04:00
David Harris
1b39481a16 TLB mux and swizzling cleanup 2021-07-04 12:53:52 -04:00
David Harris
735f3b4217 Replaced generates with arrays in TLB 2021-07-04 12:32:27 -04:00
David Harris
67e191c6f3 Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries 2021-07-04 11:39:59 -04:00
David Harris
ccd9c05303 Switched to array notation for pmpchecker 2021-07-04 10:51:56 -04:00
David Harris
accbebfa6f Commented out some unused modules 2021-07-04 01:40:27 -04:00
David Harris
e90c532258 Merge conflict on linux-waves.do 2021-07-04 01:22:10 -04:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
bbracker
d68791a6d9 optionally output GDB-formatted instruction list to main buildroot folder 2021-07-03 17:25:19 -04:00
Ross Thompson
9f16d08d0d removed mmustall and finished port annotations on ptw and lsuArb. 2021-07-03 16:06:09 -05:00
Ross Thompson
043f1e10c5 Added explicit names to lsu, lsuarb and pagetable walker to make the code refactoring process eaiser. 2021-07-03 15:51:25 -05:00
Ben Bracker
d8facacef6 src/cache/ICacheCntrl.sv 2021-07-03 11:24:41 -05:00
Ben Bracker
eff5a1b90f fix ICache indenting 2021-07-03 11:11:07 -05:00
David Harris
1fa4abf7b6 Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker 2021-07-03 03:29:33 -04:00
David Harris
d44916dacf Cleaned up PMA/PMP checker unused code 2021-07-03 02:25:31 -04:00
Ben Bracker
59b177beac stop busybear from hanging 2021-07-02 17:22:09 -05:00
David Harris
0bd18ff662 Fixed PMPCFG read faults 2021-07-02 17:08:13 -04:00
Ross Thompson
cf688bd3f6 Fixed up the physical address generation for 64 bit page table walker. 2021-07-02 15:49:32 -05:00
Ross Thompson
8e3149517a Fixed up the bit widths on the page table walker for rv32. 2021-07-02 15:45:05 -05:00
Ross Thompson
7b3716c281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Katherine Parry
20d6e57aa5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:56:53 -04:00
Katherine Parry
308c9ccaac FPU update - missing files 2021-07-02 12:53:05 -04:00
Ross Thompson
dbd33465e1 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
5b6ebd7935 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-02 12:52:20 -04:00
Katherine Parry
30ff212ca8 FPU update 2021-07-02 12:40:58 -04:00
David Harris
76a43eb468 Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:05:25 -04:00
David Harris
c85e0df1ff Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:04:13 -04:00
Ross Thompson
d1a366472f reverted change to the imperas tests order. Accidently commited change which placed the virtual memory tests first. 2021-07-01 18:04:43 -05:00
Ross Thompson
118dfa9cec added page table walker fault exit for icache. 2021-07-01 17:59:55 -05:00
Ross Thompson
61027f650c OMG. It's working! 2021-07-01 17:37:53 -05:00
Ross Thompson
6916784354 Fixed tab space issue. 2021-07-01 17:17:53 -05:00
Ross Thompson
2dc349ea6f Fixed the wrong virtual address write into the dtlb. 2021-07-01 16:55:16 -05:00
Teo Ene
ec21126474 Flow updated for 90nm 2021-07-01 13:32:42 -05:00
Ross Thompson
88a18496cf Got some stores working in virtual memory. 2021-07-01 12:49:09 -05:00
Ross Thompson
157b1b31bf Icache ITLB interlock fix. 2021-06-30 19:24:59 -05:00
Ross Thompson
002c32d2ad The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay. 2021-06-30 17:02:36 -05:00
Ross Thompson
9ec624702d Major rewrite of ptw to remove combo loop. 2021-06-30 16:25:03 -05:00
Ross Thompson
b2d8ba6742 The icache now correctly interlocks with the PTW on TLB miss. 2021-06-30 11:24:26 -05:00
Ross Thompson
dd84f2958e Page table walker now walks the table. 
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
 2021-06-29 22:33:57 -05:00
Katherine Parry
0c2b7a1132 FPU control signals changed and FMA works 2021-06-28 18:53:58 -04:00
Ross Thompson
bc9c944ba0 Don't use this branch walker still broken. 2021-06-28 17:26:11 -05:00
bbracker
751e606fb7 trying out Noah and Kaveh's proposed hack for which CSRs to update for QEMU MMU bug 2021-06-26 08:30:58 -04:00
bbracker
17afd9e5e8 temporarily disable PMP checking for EBU accesses. 2021-06-26 07:19:51 -04:00
bbracker
74833dc68c split intermediate GDB output file into smaller files for better debug experience 2021-06-26 07:18:26 -04:00
Ross Thompson
d80ebab941 AMO and LR/SC instructions now working correctly. 
Page table walking is not working.
 2021-06-25 15:42:07 -05:00
Ross Thompson
57a7074800 Some progress. Had to change how the page table walker got it's ready. 2021-06-25 15:07:41 -05:00
Ross Thompson
b4a788c341 Working through a combo loop. 2021-06-25 14:49:27 -05:00
Ross Thompson
d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
bbracker
13cf7c0934 linux testbench now ignores HWRITE glitches caused by flush glitches 2021-06-25 09:28:52 -04:00
bbracker
5b47da21ba made testbench-linux's PCDwrong be FlushD 2021-06-25 08:15:19 -04:00
bbracker
34dbad967d ah merge; I checked and this does pass all of regression except lints 2021-06-25 07:37:06 -04:00
bbracker
192171826b changed SC M-to-E fowarding to W-to-E forwarding to improve critical path 2021-06-25 07:18:38 -04:00