forked from Github_Repos/cvw
linux testbench progress
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@ -27,7 +27,7 @@
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module testbench();
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0000001; // # of instructions at which to turn on waves in graphical sim
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parameter waveOnICount = `BUSYBEAR*140000 + `BUILDROOT*0000000; // # of instructions at which to turn on waves in graphical sim
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parameter stopICount = `BUSYBEAR*143898 + `BUILDROOT*0000000; // # instructions at which to halt sim completely (set to 0 to let it run as far as it can)
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///////////////////////////////////////////////////////////////////////////////
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@ -399,7 +399,7 @@ module testbench();
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if ($time == 0) begin
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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if (dut.hart.ieu.dp.regf.rf[i] != regExpected) begin
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$display("%0t ps, PCW %x, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, PCW, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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$display("%0t ps, InstrNum %0d, PCW %x, InstrW %s: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, PCW, PCtextW, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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end else begin
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@ -410,11 +410,11 @@ module testbench();
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scan_file_rf = $fscanf(data_file_rf, "%x\n", regExpected);
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end
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if (i != regNumExpected) begin
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$display("%0t ps, PCW %x %s, instr %0d: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, PCW, PCtextW, instrs, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]);
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$display("%0t ps, InstrNum %0d, PCW %x, InstrW %s: wrong register changed: %0d, %0d expected to switch to %x from %x", $time, instrs, PCW, PCtextW, i, regNumExpected, regExpected, dut.hart.ieu.dp.regf.rf[regNumExpected]);
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`ERROR
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end
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if (~(dut.hart.ieu.dp.regf.rf[i] === regExpected)) begin
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$display("%0t ps, PCW %x %s, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, PCW, PCtextW, instrs, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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$display("%0t ps, InstrNum %0d, PCW %x, InstrW %s: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, PCW, PCtextW, i, dut.hart.ieu.dp.regf.rf[i], regExpected);
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`ERROR
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end
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end
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@ -422,9 +422,9 @@ module testbench();
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end
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endgenerate
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///////////////////////////////////////////////////////////////////////////////
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//////////////////////// Bus Unit Read/Write Checking /////////////////////////
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///////////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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//////////////////////// Memory Read/Write Checking /////////////////////////
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/////////////////////////////////////////////////////////////////////////////
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// RAM and bootram are addressed in 64-bit blocks - this logic handles R/W
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// including subwords. Brief explanation on signals:
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//
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@ -452,11 +452,9 @@ module testbench();
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// ------------
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// Read Checker
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// ------------
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always @(dut.hart.lsu.dcache.ReadDataM) begin
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#2;
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if (dut.hart.MemRWM[1]
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&& (dut.hart.ebu.CaptureDataM)
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&& dut.hart.lsu.dcache.ReadDataM !== {64{1'bx}}) begin
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always @(negedge clk) begin
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//if (dut.hart.MemRWM[1] && ~dut.hart.StallM && ~dut.hart.FlushM && dut.hart.ieu.InstrValidM) begin <-- This doesn't work because ReadDataM can be used for other things (namely page table walking) while the pipeline is stalled, leaving it in a different state when the pipeline unstalls
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if (dut.hart.MemRWM[1] && dut.hart.lsu.dcache.ReadDataWEn) begin // <-- ReadDataWEn is a good indicator that the pipeline is using the current contents of ReadDataM
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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`ERROR
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@ -465,18 +463,18 @@ module testbench();
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readDataExpected);
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assign readAdrTranslated = adrTranslator(readAdrExpected);
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if (~(dut.hart.lsu.dcache.MemPAdrM === readAdrTranslated)) begin
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$display("%0t ps, PCM %x %s, instr %0d: dut.hart.lsu.dcache.MemPAdrM does not equal readAdrExpected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.MemPAdrM, readAdrTranslated);
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$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal readAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, readAdrTranslated);
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`ERROR
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end
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if (readDataExpected !== dut.hart.lsu.dcache.ReadDataM) begin
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if (dut.hart.lsu.dcache.MemPAdrM inside `LINUX_FIX_READ) begin
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if (dut.hart.lsu.dcache.MemPAdrM != 'h10000005) // Suppress the warning for UART LSR so we can read UART output
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$display("warning %0t ps, PCM %x %s, instr %0d, adr %0d: forcing readDataExpected to expected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.MemPAdrM, readDataExpected, dut.hart.lsu.dcache.ReadDataM);
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$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s:: forcing readDataExpected to expected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, readDataExpected, dut.hart.lsu.dcache.ReadDataM);
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force dut.hart.lsu.dcache.ReadDataM = readDataExpected;
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#9;
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release dut.hart.lsu.dcache.ReadDataM;
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end else begin
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$display("%0t ps, PCM %x %s, instr %0d: ExpectedreadDataExpected does not equal dut.hart.lsu.dcache.ReadDataM: %x, %x from address %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, readDataExpected, dut.hart.lsu.dcache.ReadDataM, dut.hart.lsu.dcache.MemPAdrM);
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$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: ReadDataM does not equal readDataExpected: %x, %x from address %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.ReadDataM, readDataExpected, dut.hart.lsu.dcache.MemPAdrM);
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`ERROR
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end
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end
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@ -486,10 +484,8 @@ module testbench();
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// -------------
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// Write Checker
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// -------------
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// this might need to change
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always @(negedge dut.hart.lsu.dcache.MemRWM) begin
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//#1;
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if (($time != 0) && ~dut.hart.hzu.FlushM) begin
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always @(negedge clk) begin
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if (dut.hart.MemRWM[0] && ~dut.hart.StallM && ~dut.hart.FlushM && dut.hart.ieu.InstrValidM && ($time != 0)) begin
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if($feof(data_file_memW)) begin
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$display("no more memW data to read");
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`ERROR
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@ -499,11 +495,11 @@ module testbench();
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assign writeAdrTranslated = adrTranslator(writeAdrExpected);
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if (writeDataExpected != dut.hart.lsu.dcache.WriteDataM && ~dut.uncore.HSELPLICD) begin
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$display("%0t ps, PCM %x %s, instr %0d: dut.hart.lsu.dcache.WriteDataM does not equal writeDataExpected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.WriteDataM, writeDataExpected);
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$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: WriteDataM does not equal writeDataExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.WriteDataM, writeDataExpected);
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`ERROR
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end
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if (~(writeAdrTranslated === dut.hart.lsu.dcache.MemPAdrM) && ~dut.uncore.HSELPLICD) begin
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$display("%0t ps, PCM %x %s, instr %0d: dut.hart.lsu.dcache.MemPAdrM does not equal writeAdrExpected: %x, %x", $time, dut.hart.ifu.PCM, PCtextM, instrs, dut.hart.lsu.dcache.MemPAdrM, writeAdrTranslated);
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$display("%0t ps, InstrNum %0d, PCM %x, InstrM %s: MemPAdrM does not equal writeAdrExpected: %x, %x", $time, instrs, dut.hart.ifu.PCM, PCtextM, dut.hart.lsu.dcache.MemPAdrM, writeAdrTranslated);
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`ERROR
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end
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end
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