Array of muxes in tlbmixer; abbreviated PPN and VPN to match diagram

wally-pipelined/src/mmu/tlb.sv

@@ -93,8 +93,8 @@ module tlb #(parameter TLB_ENTRIES = 8,
   logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex
 
   // Sections of the virtual and physical addresses
-  logic [`VPN_BITS-1:0] VirtualPageNumber;
-  logic [`PPN_BITS-1:0] PhysicalPageNumber;
+  logic [`VPN_BITS-1:0] VPN;
+  logic [`PPN_BITS-1:0] PPN;
   logic [`XLEN+1:0]     AddressExt;
 
   // Sections of the page table entry
@@ -106,7 +106,7 @@ module tlb #(parameter TLB_ENTRIES = 8,
   logic                  CAMHit;
   logic                  SV39Mode;
 
-  assign VirtualPageNumber = Address[`VPN_BITS+11:12];
+  assign VPN = Address[`VPN_BITS+11:12];
 
   tlbcontrol tlbcontrol(.SATP_MODE, .Address, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
                         .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush,
@@ -115,13 +115,13 @@ module tlb #(parameter TLB_ENTRIES = 8,
 
   tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables);
   tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) 
-    tlbcam(.clk, .reset, .VirtualPageNumber, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, 
+    tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, 
            .SATP_ASID, .Matches, .HitPageType, .CAMHit);
-  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PhysicalPageNumber, .PTEAccessBits, .PTE_Gs);
+  tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs);
 
   // Replace segments of the virtual page number with segments of the physical
   // page number. For 4 KB pages, the entire virtual page number is replaced.
   // For superpages, some segments are considered offsets into a larger page.
-  tlbmixer Mixer(.VirtualPageNumber, .PhysicalPageNumber, .HitPageType, .Address(Address[11:0]), .TLBHit, .TLBPAdr);
+  tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Address(Address[11:0]), .TLBHit, .TLBPAdr);
 
 endmodule

wally-pipelined/src/mmu/tlbcam.sv

@@ -32,7 +32,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
                 parameter KEY_BITS   = 20,
                 parameter SEGMENT_BITS = 10) (
   input logic                     clk, reset,
-  input logic [`VPN_BITS-1:0]     VirtualPageNumber,
+  input logic [`VPN_BITS-1:0]     VPN,
   input logic [1:0]               PageTypeWriteVal,
   input  logic                    SV39Mode,
   input logic                     TLBFlush,
@@ -53,7 +53,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8,
   // page number segments.
 
   tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0](
-    .clk, .reset, .VirtualPageNumber, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush,
+    .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush,
     .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches));
   assign CAMHit = |Matches & ~TLBFlush;
   assign HitPageType = PageTypeRead.or; // applies OR to elements of the (TLB_ENTRIES x 2) array to get 2-bit result

wally-pipelined/src/mmu/tlbcamline.sv

@@ -31,7 +31,7 @@
 module tlbcamline #(parameter KEY_BITS = 20,
                     parameter SEGMENT_BITS = 10) (
   input  logic                  clk, reset,
-  input  logic [`VPN_BITS-1:0]  VirtualPageNumber, // The requested page number to compare against the key
+  input  logic [`VPN_BITS-1:0]  VPN, // The requested page number to compare against the key
   input  logic [`ASID_BITS-1:0] SATP_ASID,
   input  logic                  SV39Mode,
   input  logic                  WriteEnable,  // Write a new entry to this line
@@ -64,7 +64,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
     if (`XLEN == 32) begin
 
       assign {Key_ASID, Key1, Key0} = Key;
-      assign {Query1, Query0} = VirtualPageNumber;
+      assign {Query1, Query0} = VPN;
 
       // Calculate the actual match value based on the input vpn and the page type.
       // For example, a megapage in SV32 only cares about VPN[1], so VPN[0]
@@ -78,7 +78,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
       logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3;
       logic Match2, Match3;
 
-      assign {Query3, Query2, Query1, Query0} = VirtualPageNumber;
+      assign {Query3, Query2, Query1, Query0} = VPN;
       assign {Key_ASID, Key3, Key2, Key1, Key0} = Key;
 
       // Calculate the actual match value based on the input vpn and the page type.
@@ -102,5 +102,5 @@ module tlbcamline #(parameter KEY_BITS = 20,
   // *** Might we want to update stored key right away to output match on the
   // write cycle? (using a mux)
   flopenrc #(1) validbitflop(clk, reset, TLBFlush, WriteEnable, 1'b1, Valid);
-  flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VirtualPageNumber}, Key);
+  flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key);
 endmodule

wally-pipelined/src/mmu/tlbram.sv

@@ -31,7 +31,7 @@ module tlbram #(parameter TLB_ENTRIES = 8) (
   input  logic                      clk, reset,
   input  logic [`XLEN-1:0]          PTE,
   input  logic [TLB_ENTRIES-1:0]    Matches, WriteEnables,
-  output logic [`PPN_BITS-1:0]      PhysicalPageNumber,
+  output logic [`PPN_BITS-1:0]      PPN,
   output logic [7:0]                PTEAccessBits,
   output logic [TLB_ENTRIES-1:0]    PTE_Gs
 );
@@ -44,5 +44,5 @@ module tlbram #(parameter TLB_ENTRIES = 8) (
   
   assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
   assign PTEAccessBits = PageTableEntry[7:0];
-  assign PhysicalPageNumber = PageTableEntry[`PPN_BITS+9:10];
+  assign PPN = PageTableEntry[`PPN_BITS+9:10];
 endmodule