forked from Github_Repos/cvw
Progress towards the test bench flush.
This commit is contained in:
Ross Thompson
parent
f26d635614
commit
1cc258ade1
@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
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add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
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add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
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add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
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add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
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add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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@ -250,25 +250,25 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/genblk1[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
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add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
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@ -280,7 +280,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
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@ -295,8 +294,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetValidW
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {SRAM Write} /testbench/dut/hart/lsu/dcache/SetDirtyW
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add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM
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@ -396,8 +393,8 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
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add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
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add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 4} {2797 ns} 0} {{Cursor 6} {3275 ns} 0} {{Cursor 8} {3905 ns} 0} {{Cursor 9} {4358 ns} 0} {{Cursor 10} {5007 ns} 0} {{Cursor 11} {57795 ns} 0}
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quietly wave cursor active 6
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WaveRestoreCursors {{Cursor 12} {57781 ns} 0} {{Cursor 13} {7061 ns} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 273
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configure wave -justifyvalue left
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@ -412,4 +409,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {57593 ns} {57969 ns}
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WaveRestoreZoom {57704 ns} {58248 ns}
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2
wally-pipelined/src/cache/DCacheMem.sv
vendored
2
wally-pipelined/src/cache/DCacheMem.sv
vendored
@ -53,7 +53,7 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
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genvar words;
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generate
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for(words = 0; words < BLOCKLEN/`XLEN; words++) begin
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for(words = 0; words < BLOCKLEN/`XLEN; words++) begin : word
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sram1rw #(.DEPTH(`XLEN),
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.WIDTH(NUMLINES))
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CacheDataMem(.clk(clk),
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@ -44,14 +44,14 @@ module testbench();
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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//string tests32mmu[] = '{
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//"rv32mmu/WALLY-MMU-SV32", "3000"
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// };
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string tests32mmu[] = '{
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"rv32mmu/WALLY-MMU-SV32", "3000"
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};
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//string tests64mmu[] = '{
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//"rv64mmu/WALLY-MMU-SV48", "3000",
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//"rv64mmu/WALLY-MMU-SV39", "3000"
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//};
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string tests64mmu[] = '{
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"rv64mmu/WALLY-MMU-SV48", "3000",
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"rv64mmu/WALLY-MMU-SV39", "3000"
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};
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string tests32f[] = '{
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@ -216,6 +216,7 @@ string tests32f[] = '{
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string tests64i[] = '{
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//"rv64i/WALLY-PIPELINE-100K", "f7ff0",
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//"rv64i/WALLY-LOAD", "11bf0",
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"rv64i/I-ADD-01", "3000",
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"rv64i/I-ADDI-01", "3000",
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"rv64i/I-ADDIW-01", "3000",
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@ -286,7 +287,7 @@ string tests32f[] = '{
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"rv64i/WALLY-SLLI", "3000",
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"rv64i/WALLY-SRLI", "3000",
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"rv64i/WALLY-SRAI", "3000",
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"rv64i/WALLY-LOAD", "11bf0",
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"rv64i/WALLY-JAL", "4000",
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"rv64i/WALLY-JALR", "3000",
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"rv64i/WALLY-STORE", "3000",
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@ -513,6 +514,9 @@ string tests32f[] = '{
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logic HCLK, HRESETn;
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logic [`XLEN-1:0] PCW;
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logic DCacheFlushDone, DCacheFlushStart;
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logic [`XLEN-1:0] debug;
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assign debug = dut.uncore.dtim.RAM[536872960];
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@ -540,9 +544,10 @@ string tests32f[] = '{
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else tests = {tests, tests64iNOc};
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||||
if (`M_SUPPORTED) tests = {tests, tests64m};
|
||||
if (`A_SUPPORTED) tests = {tests, tests64a};
|
||||
//if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||
tests = {tests64i, tests};
|
||||
end
|
||||
//tests = {tests64a, tests};
|
||||
end else begin // RV32
|
||||
@ -625,9 +630,9 @@ string tests32f[] = '{
|
||||
// check results
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||
if (DCacheFlushDone) begin
|
||||
$display("Code ended with ecall with gp = 1");
|
||||
|
||||
#60; // give time for instructions in pipeline to finish
|
||||
// clear signature to prevent contamination from previous tests
|
||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||
@ -706,6 +711,18 @@ string tests32f[] = '{
|
||||
.ProgramLabelMapFile(ProgramLabelMapFile));
|
||||
end
|
||||
|
||||
assign DCacheFlushStart = dut.hart.priv.EcallFaultM &&
|
||||
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||
(dut.hart.ieu.dp.regf.we3 &&
|
||||
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||
dut.hart.ieu.dp.regf.wd3 == 1));
|
||||
|
||||
DCacheFlushFSM DCacheFlushFSM(.clk(clk),
|
||||
.reset(reset),
|
||||
.start(DCacheFlushStart),
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
|
||||
generate
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1) begin : bpred
|
||||
@ -959,5 +976,206 @@ module logging(
|
||||
|
||||
always @(posedge clk)
|
||||
if (HTRANS != 2'b00 && HADDR == 0)
|
||||
$display("Warning: access to memory address 0\n");
|
||||
$display("%t Warning: access to memory address 0\n", $realtime);
|
||||
endmodule
|
||||
|
||||
|
||||
module DCacheFlushFSM
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic start,
|
||||
output logic done);
|
||||
|
||||
localparam integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||
localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
localparam integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer logblockbytelen = $clog2(blockbytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||
|
||||
|
||||
typedef enum {IDLE,
|
||||
READ,
|
||||
DONE} statetype;
|
||||
|
||||
statetype CurrState, NextState;
|
||||
|
||||
logic CountFlag;
|
||||
logic CntEn;
|
||||
|
||||
logic [lognumways + lognumlines - 1 : 0] count, countNext;
|
||||
|
||||
flopenr #(lognumlines + lognumways)
|
||||
FetchCountReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(CntEn),
|
||||
.d(countNext),
|
||||
.q(count));
|
||||
|
||||
assign countNext = count + 1;
|
||||
assign CountFlag = count == '1;
|
||||
|
||||
always_ff @(posedge clk, posedge reset) begin
|
||||
if(reset) CurrState = IDLE;
|
||||
else CurrState = NextState;
|
||||
end
|
||||
|
||||
always_comb begin
|
||||
case (CurrState)
|
||||
IDLE: if(start) NextState = READ;
|
||||
else NextState = IDLE;
|
||||
READ: begin
|
||||
force testbench.dut.hart.lsu.dcache.SRAMAdr = count;
|
||||
if(CountFlag) begin
|
||||
NextState = DONE;
|
||||
end else begin
|
||||
NextState = READ;
|
||||
end
|
||||
end
|
||||
DONE: begin
|
||||
release testbench.dut.hart.lsu.dcache.SRAMAdr;
|
||||
NextState = DONE;
|
||||
end
|
||||
default: NextState = IDLE;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign done = CurrState == DONE;
|
||||
assign CntEn = CurrState == READ;
|
||||
|
||||
|
||||
integer adr;
|
||||
integer tag;
|
||||
integer index;
|
||||
integer way;
|
||||
integer word;
|
||||
|
||||
logic dirty, valid;
|
||||
|
||||
always_comb begin
|
||||
if (CurrState == READ) begin
|
||||
assign index = count / numways;
|
||||
assign way = count % numways;
|
||||
assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way];
|
||||
assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way];
|
||||
assign valid = testbench.dut.hart.lsu.dcache.Valid[way];
|
||||
assign adr = tag << (tagstart) + index;
|
||||
|
||||
$display("Index Way Tag V D %03x %d %016x %d %d %016x", index, way, tag, valid, dirty, adr);
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
task FlushDCache;
|
||||
// takes no inputs or ouptuts but controls logics in the d cache.
|
||||
|
||||
// two possible implementations.
|
||||
// 1) Can directly read/set the cache SRAM and the dtim.
|
||||
// The problem here is the structure of the cache is
|
||||
// not really easily known.
|
||||
// 2) Use the cache's interface to read out blocks.
|
||||
// The problem is we must do this over clock cycles.
|
||||
// Honestly not sure which is easier.
|
||||
// I don't think method 1 is possible because verilog cannot convert a string into
|
||||
// an object's hierarchy or it is not possible because verilog cannot use
|
||||
// variable index inside a generate block.
|
||||
|
||||
// path to d cache parameterization
|
||||
//sim:/testbench/dut/hart/lsu/dcache/NUMLINES
|
||||
//sim:/testbench/dut/hart/lsu/dcache/NUMWAYS
|
||||
//sim:/testbench/dut/hart/lsu/dcache/BLOCKBYTELEN
|
||||
|
||||
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData
|
||||
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData
|
||||
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits
|
||||
//sim:/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits
|
||||
|
||||
static string GenericCacheDataMem = "testbench.dut.hart.lsu.dcache.CacheWays[%0d].MemWay.word[%0d].CacheDataMem.StoredData[%0d]";
|
||||
static string GenericCacheTagMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.CacheTagMem.StoredData[%d]";
|
||||
static string GenericCacheValidMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.ValidBits[%d]";
|
||||
static string GenericCacheDirtyMem = "testbench.dut.hart.lsu.dcache.CacheWays[%d].MemWay.DirtyBits[%d]";
|
||||
|
||||
|
||||
|
||||
const integer numlines = testbench.dut.hart.lsu.dcache.NUMLINES;
|
||||
const integer numways = testbench.dut.hart.lsu.dcache.NUMWAYS;
|
||||
const integer blockbytelen = testbench.dut.hart.lsu.dcache.BLOCKBYTELEN;
|
||||
const integer numwords = testbench.dut.hart.lsu.dcache.BLOCKLEN/`XLEN;
|
||||
const integer lognumlines = $clog2(numlines);
|
||||
const integer logblockbytelen = $clog2(blockbytelen);
|
||||
const integer tagstart = lognumlines + logblockbytelen;
|
||||
|
||||
|
||||
|
||||
// drive SRAMAdr
|
||||
//sim:/testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||
// Read ReadTag and then mux out on the NUMWAYS
|
||||
//sim:/testbench/dut/hart/lsu/dcache/ReadTag
|
||||
//sim:/testbench/dut/hart/lsu/dcache/Valid
|
||||
//sim:/testbench/dut/hart/lsu/dcache/Dirty
|
||||
|
||||
// if Valid and Dirty we write to dtim
|
||||
|
||||
logic [`PA_BITS-1:0] FullAdr;
|
||||
|
||||
integer adr;
|
||||
integer tag;
|
||||
integer index;
|
||||
integer way;
|
||||
integer word;
|
||||
|
||||
logic dirty, valid;
|
||||
|
||||
logic [`XLEN-1:0] value;
|
||||
|
||||
|
||||
|
||||
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
$display("%d %d", tagstart, logblockbytelen);
|
||||
|
||||
|
||||
for(adr = 0; adr < numways * numlines; adr++) begin
|
||||
assign way = adr % numways;
|
||||
assign index = adr / numways;
|
||||
force testbench.dut.hart.lsu.dcache.SRAMAdr = index;
|
||||
assign tag = testbench.dut.hart.lsu.dcache.ReadTag[way];
|
||||
assign dirty = testbench.dut.hart.lsu.dcache.Dirty[way];
|
||||
assign valid = testbench.dut.hart.lsu.dcache.Valid[way];
|
||||
assign FullAdr = tag<<tagstart;
|
||||
|
||||
|
||||
$display("Index Way Tag V D %03x %d %016x %d %d Full Adr %08x", index, way, tag, valid, dirty, FullAdr);
|
||||
end
|
||||
|
||||
|
||||
release testbench.dut.hart.lsu.dcache.SRAMAdr;
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
static string path;
|
||||
logic [`XLEN-1:0] CacheData;
|
||||
|
||||
assign value = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[0];
|
||||
|
||||
for(index = 0; index < numlines; index++) begin
|
||||
for(way = 0; way < numways; way++) begin
|
||||
for(word = 0; word < numwords; word++) begin
|
||||
assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index];
|
||||
|
||||
path = $sformatf(GenericCacheDataMem, way, word, index);
|
||||
// I guess you cannot do this conversion.
|
||||
//assign CacheData = path;
|
||||
$display("%x", path);
|
||||
$display(CacheData);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
$display("%x", value);
|
||||
|
||||
|
||||
|
||||
endtask
|
||||
|
||||
Loading…
Reference in New Issue
Block a user