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Added ASID matching for CAM

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This commit is contained in:
David Harris 2021-07-06 18:56:25 -04:00
parent 7d857cf4bd
commit af619dcd75
1 changed files with 2 additions and 2 deletions
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4
wally-pipelined/src/mmu/tlbcamline.sv
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@ -72,7 +72,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
assign Match0 = (Query0 == Key0) || (PageType[0]); // least signifcant section
assign Match1 = (Query1 == Key1);
assign Match = Match0 & Match1 & Valid;
assign Match = Match0 & Match1 & MatchASID & Valid;
end else begin
logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3;
@ -89,7 +89,7 @@ module tlbcamline #(parameter KEY_BITS = 20,
assign Match2 = (Query2 == Key2) || (PageType > 2'd2);
assign Match3 = (Query3 == Key3) || SV39Mode; // this should always match in sv39 because they aren't used
assign Match = Match0 & Match1 & Match2 & Match3 & Valid;
assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid;
end
endgenerate