forked from Github_Repos/cvw
Partially working changes to support uncached memory access. Not sure what CommitedM is.
This commit is contained in:
Ross Thompson
parent
baa2b5d15f
commit
3e57c899a2
@ -239,22 +239,22 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetValid}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/SetDirty}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/Adr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/WAdr}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/CacheTagMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/DirtyBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/ValidBits}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[0]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[1]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
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add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
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@ -272,8 +272,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
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@ -290,6 +288,15 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memo
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
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add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/BasePAdrM
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
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add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
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add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
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add wave -noupdate -expand -group lsu -group old -color Gold /testbench/dut/hart/lsu/CurrState
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/DisableTranslation
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add wave -noupdate -expand -group lsu -group old /testbench/dut/hart/lsu/MemRWM
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@ -312,20 +319,20 @@ add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HRESPPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/HREADYPLIC
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add wave -noupdate -group plic /testbench/dut/uncore/genblk2/plic/ExtIntM
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
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add wave -noupdate -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HCLK
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HSELGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HADDR
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWDATA
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HWRITE
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADY
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HTRANS
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HRESPGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/HREADYGPIO
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsIn
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsOut
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOPinsEn
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add wave -noupdate -expand -group GPIO /testbench/dut/uncore/genblk3/gpio/GPIOIntr
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HCLK
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HSELCLINT
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add wave -noupdate -group CLINT /testbench/dut/uncore/genblk1/clint/HADDR
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@ -394,8 +401,8 @@ add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
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add wave -noupdate /testbench/dut/uncore/dtim/memwrite
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add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 12} {1978950 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {2053811 ns} 0}
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quietly wave cursor active 2
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WaveRestoreCursors {{Cursor 12} {4707 ns} 0} {{Cursor 4} {1979605 ns} 0} {{Cursor 5} {6253401 ns} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 250
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configure wave -valuecolwidth 297
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configure wave -justifyvalue left
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@ -410,4 +417,4 @@ configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {1979564 ns} {1979828 ns}
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WaveRestoreZoom {4642 ns} {4816 ns}
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47
wally-pipelined/src/cache/dcache.sv
vendored
47
wally-pipelined/src/cache/dcache.sv
vendored
@ -48,7 +48,7 @@ module dcache
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// inputs from TLB and PMA/P
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input logic FaultM,
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input logic DTLBMissM,
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input logic UncachedM,
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input logic CacheableM,
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// ahb side
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output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
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output logic AHBRead,
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@ -114,6 +114,8 @@ module dcache
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logic [2**LOGWPL-1:0] MemPAdrDecodedW;
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logic [`PA_BITS-1:0] BasePAdrM;
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logic [OFFSETLEN-1:0] BasePAdrOffsetM;
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logic [`PA_BITS-1:0] BasePAdrMaskedM;
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logic [TAGLEN-1:0] VictimTagWay [NUMWAYS-1:0];
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logic [TAGLEN-1:0] VictimTag;
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@ -224,7 +226,7 @@ module dcache
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// variable input mux
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assign ReadDataWordM = ReadDataBlockSetsM[MemPAdrM[$clog2(WORDSPERLINE+`XLEN/8) : $clog2(`XLEN/8)]];
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assign HWDATA = VictimReadDataBlockSetsM[FetchCount];
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assign HWDATA = CacheableM ? VictimReadDataBlockSetsM[FetchCount] : WriteDataM;
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// finally swr
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// *** BUG fix HSIZED? why was it this way?
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@ -271,14 +273,17 @@ module dcache
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// *** optimize this
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mux2 #(`PA_BITS) BaseAdrMux(.d0(MemPAdrM),
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.d1({VictimTag, MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
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.s(AHBWrite),
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.s(AHBWrite & CacheableM),
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.y(BasePAdrM));
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assign BasePAdrOffsetM = CacheableM ? {{OFFSETLEN}{1'b0}} : BasePAdrM[OFFSETLEN-1:0];
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assign BasePAdrMaskedM = {BasePAdrM[`PA_BITS-1:OFFSETLEN], BasePAdrOffsetM};
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generate
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if (`XLEN == 32) begin
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assign AHBPAdr = ({ {`PA_BITS-4{1'b0}}, FetchCount} << 2) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};
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assign AHBPAdr = ({{`PA_BITS-4{1'b0}}, FetchCount} << 2) + BasePAdrMaskedM;
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end else begin
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assign AHBPAdr = ({ {`PA_BITS-3{1'b0}}, FetchCount} << 3) + {BasePAdrM[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}};
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assign AHBPAdr = ({{`PA_BITS-3{1'b0}}, FetchCount} << 3) + BasePAdrMaskedM;
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end
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endgenerate
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@ -339,6 +344,8 @@ module dcache
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STATE_PTW_MISS_READ_SRAM,
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STATE_UNCACHED_WDV,
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STATE_UNCACHED_DONE,
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STATE_UNCACHED_WRITE,
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STATE_UNCACHED_WRITE_DONE,
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STATE_CPU_BUSY} statetype;
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statetype CurrState, NextState;
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@ -398,7 +405,7 @@ module dcache
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NextState = STATE_PTW_MISS_FETCH_WDV;
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end
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// amo hit
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else if(|AtomicM & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin
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else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
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NextState = STATE_AMO_UPDATE;
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DCacheStall = 1'b1;
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@ -406,7 +413,7 @@ module dcache
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else NextState = STATE_READY;
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end
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// read hit valid cached
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else if(MemRWM[1] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin
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else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
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NextState = STATE_READY;
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DCacheStall = 1'b0;
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@ -414,7 +421,7 @@ module dcache
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else NextState = STATE_READY;
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end
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// write hit valid cached
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else if (MemRWM[0] & ~UncachedM & ~FaultM & CacheHit & ~DTLBMissM) begin
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else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
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SelAdrM = 1'b1;
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DCacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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@ -424,11 +431,19 @@ module dcache
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else NextState = STATE_READY;
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end
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// read or write miss valid cached
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else if((|MemRWM) & ~UncachedM & ~FaultM & ~CacheHit & ~DTLBMissM) begin
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else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin
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NextState = STATE_MISS_FETCH_WDV;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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end
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// uncached write
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else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
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NextState = STATE_UNCACHED_WRITE;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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AHBWrite = 1'b1;
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end
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// fault
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||||
else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin
|
||||
NextState = STATE_READY;
|
||||
@ -529,6 +544,20 @@ module dcache
|
||||
if(StallW) NextState = STATE_CPU_BUSY;
|
||||
else NextState = STATE_READY;
|
||||
end
|
||||
|
||||
STATE_UNCACHED_WRITE : begin
|
||||
DCacheStall = 1'b1;
|
||||
AHBWrite = 1'b1;
|
||||
if(AHBAck) begin
|
||||
NextState = STATE_UNCACHED_WRITE_DONE;
|
||||
end else begin
|
||||
NextState = STATE_UNCACHED_WRITE;
|
||||
end
|
||||
end
|
||||
|
||||
STATE_UNCACHED_WRITE_DONE: begin
|
||||
NextState = STATE_READY;
|
||||
end
|
||||
default: begin
|
||||
end
|
||||
endcase
|
||||
|
||||
@ -136,6 +136,9 @@ module ifu (
|
||||
.LoadAccessFaultM(),
|
||||
.StoreAccessFaultM(),
|
||||
.DisableTranslation(1'b0),
|
||||
.Cacheable(),
|
||||
.Idempotent(),
|
||||
.AtomicAllowed(),
|
||||
.*);
|
||||
|
||||
|
||||
|
||||
@ -62,12 +62,13 @@ module lsu
|
||||
|
||||
// connect to ahb
|
||||
input logic CommitM, // should this be generated in the abh interface?
|
||||
output logic [`PA_BITS-1:0] DCtoAHBPAdrM, // to ahb
|
||||
output logic [`PA_BITS-1:0] DCtoAHBPAdrM,
|
||||
output logic DCtoAHBReadM,
|
||||
output logic DCtoAHBWriteM,
|
||||
input logic DCfromAHBAck, // from ahb
|
||||
input logic [`XLEN-1:0] DCfromAHBReadData, // from ahb
|
||||
output logic [`XLEN-1:0] DCtoAHBWriteData, // to ahb
|
||||
input logic DCfromAHBAck,
|
||||
input logic [`XLEN-1:0] DCfromAHBReadData,
|
||||
output logic [`XLEN-1:0] DCtoAHBWriteData,
|
||||
output logic [2:0] DCtoAHBSizeM,
|
||||
|
||||
// mmu management
|
||||
|
||||
@ -140,8 +141,8 @@ module lsu
|
||||
logic HPTWReady;
|
||||
logic DisableTranslation; // used to stop intermediate PTE physical addresses being saved to TLB.
|
||||
logic DCacheStall;
|
||||
|
||||
|
||||
|
||||
logic CacheableM;
|
||||
|
||||
pagetablewalker pagetablewalker(
|
||||
.clk(clk),
|
||||
@ -223,9 +224,19 @@ module lsu
|
||||
.SquashBusAccess(),
|
||||
.DisableTranslation(DisableTranslation),
|
||||
.InstrAccessFaultF(),
|
||||
.Cacheable(CacheableM),
|
||||
.Idempotent(),
|
||||
.AtomicAllowed(),
|
||||
// .SelRegions(DHSELRegionsM),
|
||||
.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
|
||||
|
||||
|
||||
generate
|
||||
if (`XLEN == 32) assign DCtoAHBSizeM = CacheableM ? 3'b010 : Funct3MtoDCache;
|
||||
else assign DCtoAHBSizeM = CacheableM ? 3'b011 : Funct3MtoDCache;
|
||||
endgenerate;
|
||||
|
||||
|
||||
// Specify which type of page fault is occurring
|
||||
assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoDCache[1];
|
||||
assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoDCache[0];
|
||||
@ -310,7 +321,7 @@ module lsu
|
||||
.DCacheStall(DCacheStall),
|
||||
.FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults.
|
||||
.DTLBMissM(DTLBMissM),
|
||||
.UncachedM(1'b0), // ***connect to PMA
|
||||
.CacheableM(CacheableM),
|
||||
|
||||
// AHB connection
|
||||
.AHBPAdr(DCtoAHBPAdrM),
|
||||
|
||||
@ -60,6 +60,7 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
|
||||
output logic [`PA_BITS-1:0] PhysicalAddress,
|
||||
output logic TLBMiss,
|
||||
output logic TLBHit,
|
||||
output logic Cacheable, Idempotent, AtomicAllowed,
|
||||
|
||||
// Faults
|
||||
output logic TLBPageFault,
|
||||
@ -76,7 +77,6 @@ module mmu #(parameter TLB_ENTRIES = 8, // nuber of TLB Entries
|
||||
);
|
||||
|
||||
logic PMPSquashBusAccess, PMASquashBusAccess;
|
||||
logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
|
||||
// Translation lookaside buffer
|
||||
|
||||
logic PMAInstrAccessFaultF, PMPInstrAccessFaultF;
|
||||
|
||||
@ -196,6 +196,7 @@ module wallypipelinedhart
|
||||
.DCfromAHBAck(DCfromAHBAck),
|
||||
.DCfromAHBReadData(DCfromAHBReadData),
|
||||
.DCtoAHBWriteData(DCtoAHBWriteData),
|
||||
.DCtoAHBSizeM(DCtoAHBSizeM),
|
||||
|
||||
// connect to csr or privilege and stay the same.
|
||||
.PrivilegeModeW(PrivilegeModeW), // connects to csr
|
||||
@ -231,10 +232,6 @@ module wallypipelinedhart
|
||||
.LSUStall(DCacheStall)); // change to DCacheStall
|
||||
|
||||
|
||||
generate
|
||||
if (`XLEN == 32) assign DCtoAHBSizeM = 3'b010;
|
||||
else assign DCtoAHBSizeM = 3'b011;
|
||||
endgenerate;
|
||||
|
||||
|
||||
ahblite ebu(// IFU connections
|
||||
|
||||
@ -547,7 +547,6 @@ string tests32f[] = '{
|
||||
if (`MEM_VIRTMEM) tests = {tests, tests64mmu};
|
||||
if (`F_SUPPORTED) tests = {tests64f, tests};
|
||||
if (`D_SUPPORTED) tests = {tests64d, tests};
|
||||
tests = {tests64i, tests};
|
||||
end
|
||||
//tests = {tests64a, tests};
|
||||
end else begin // RV32
|
||||
|
||||
Loading…
Reference in New Issue
Block a user